МАРСОХОД

Open Source Hardware Project

Исходный код ПЛИС внутри ПЛИС

  1.  
  2. //serially programmable look-up table
  3. module lut(
  4.     input wire  ldclk, //clock used for image loading
  5.     input wire  ldi,   //lut load data input
  6.     output wire ldo,   //lut load data output
  7.     input wire  lds,   //lut load data signal
  8.    
  9.     input wire [3:0]in,
  10.     output wire out
  11. );
  12.  
  13. reg [15:0]lut_reg;
  14. always @(posedge ldclk)
  15.     if(lds)
  16.         lut_reg <= { lut_reg[14:0],ldi };
  17.  
  18. assign ldo = lut_reg[15];
  19. assign out = lut_reg[in];
  20.  
  21. endmodule
  22.  
  23. //serially programmable multiplexor
  24. module pmux8(
  25.     input wire  ldclk, //clock used for image loading
  26.     input wire  ldi, //load data input
  27.     output wire ldo, //load data output
  28.     input wire  lds, //load data signal
  29.    
  30.     input wire  [7:0]in,
  31.     output wire out
  32. );
  33.  
  34. reg [2:0]sel_reg;
  35. always @(posedge ldclk)
  36.     if(lds)
  37.         sel_reg <= { sel_reg[1:0],ldi };
  38.  
  39. assign ldo = sel_reg[2];
  40. assign out = (in[sel_reg] & (~lds));
  41.  
  42. endmodule
  43.  
  44. //serially programmable multiplexor
  45. module pmux4(
  46.     input wire  ldclk, //clock used for image loading
  47.     input wire  ldi, //load data input
  48.     output wire ldo, //load data output
  49.     input wire  lds, //load data signal
  50.    
  51.     input wire  [3:0]in,
  52.     output wire out
  53. );
  54.  
  55. reg [1:0]sel_reg;
  56. always @(posedge ldclk)
  57.     if(lds)
  58.         sel_reg <= { sel_reg[0],ldi };
  59.  
  60. assign ldo = sel_reg[1];
  61. assign out = (in[sel_reg] & (~lds));
  62.  
  63. endmodule
  64.  
  65. //logic element
  66. module le(
  67.     input wire  ldclk,
  68.     input wire  ldi, //load data input
  69.     output wire ldo, //load data output
  70.     input wire  lds, //load data signal
  71.  
  72.     input wire  sysclk,
  73.     input wire  [3:0]in,
  74.     input wire  rena,
  75.     output wire rout, //reg out
  76.     output wire lout, //lut out
  77.     output wire pout  //pin out
  78. );
  79.  
  80. wire lut_load_out;
  81. wire lut_out;
  82. lut lut_inst(
  83.     .ldclk(ldclk),
  84.     .ldi(ldi),
  85.     .ldo(lut_load_out),
  86.     .lds(lds),
  87.     .in(in),
  88.     .out(lut_out)
  89. );
  90.  
  91. reg le_reg;
  92. always @(posedge sysclk or posedge lds)
  93.     if(lds)
  94.         le_reg <= 0;
  95.     else
  96.     if(rena)
  97.         le_reg <= lout;
  98.  
  99. reg pin_ctrl;
  100. always @(posedge ldclk)
  101.     if(lds)
  102.         pin_ctrl <= lut_load_out;
  103.  
  104. assign ldo = pin_ctrl;
  105. assign lout = lut_out &(~lds);
  106. assign pout = pin_ctrl ? rout : lout;
  107. assign rout = le_reg;
  108.  
  109. endmodule
  110.  
  111. module mini_cpld(
  112.     input wire  ldclk,
  113.     input wire  ldi, //load data input
  114.     output reg  ldo, //load data output
  115.     input wire  lds, //load data signal
  116.  
  117.     input wire clk,
  118.     input wire [3:0]in_pin,
  119.     output wire [3:0]out_pin
  120. );
  121.  
  122. // Logic Element #0 and connections
  123.  
  124. //multiplexer for LE0 clk: can select from 3 regs output or system clock
  125. wire serial_img0;
  126. wire sysclk0;
  127. pmux4 pmux_inst_clk0(
  128.     .ldclk(ldclk),
  129.     .ldi(ldi),
  130.     .ldo(serial_img0),
  131.     .lds(lds),
  132.     .in( {clk, rout1, rout2, rout3} ),
  133.     .out(sysclk0)
  134.     );
  135.  
  136. wire serial_img1;
  137. wire rena0;
  138. pmux8 pmux_inst_ena0(
  139.     .ldclk(ldclk),
  140.     .ldi(serial_img0),
  141.     .ldo(serial_img1),
  142.     .lds(lds),
  143.     .in( {in_pin[0], lout1, lout2, lout3, 1'b1, rout1, rout2, rout3} ),
  144.     .out(rena0)
  145.     );
  146.  
  147. wire serial_img2;
  148. wire lut0_in0;
  149. pmux8 pmux_inst_lut00(
  150.     .ldclk(ldclk),
  151.     .ldi(serial_img1),
  152.     .ldo(serial_img2),
  153.     .lds(lds),
  154.     .in( {in_pin[0], lout1, lout2, lout3, rout0, rout1, rout2, rout3} ),
  155.     .out(lut0_in0)
  156.     );
  157.  
  158. wire serial_img3;
  159. wire lut0_in1;
  160. pmux8 pmux_inst_lut01(
  161.     .ldclk(ldclk),
  162.     .ldi(serial_img2),
  163.     .ldo(serial_img3),
  164.     .lds(lds),
  165.     .in( {in_pin[1], lout1, lout2, lout3, rout0, rout1, rout2, rout3} ),
  166.     .out(lut0_in1)
  167.     );
  168.  
  169. wire serial_img4;
  170. wire lut0_in2;
  171. pmux8 pmux_inst_lut02(
  172.     .ldclk(ldclk),
  173.     .ldi(serial_img3),
  174.     .ldo(serial_img4),
  175.     .lds(lds),
  176.     .in( {in_pin[2], lout1, lout2, lout3, rout0, rout1, rout2, rout3} ),
  177.     .out(lut0_in2)
  178.     );
  179.  
  180. wire serial_img5;
  181. wire lut0_in3;
  182. pmux8 pmux_inst_lut03(
  183.     .ldclk(ldclk),
  184.     .ldi(serial_img4),
  185.     .ldo(serial_img5),
  186.     .lds(lds),
  187.     .in( {in_pin[3], lout1, lout2, lout3, rout0, rout1, rout2, rout3} ),
  188.     .out(lut0_in3)
  189.     );
  190.  
  191. wire serial_img6;
  192. wire rout0, lout0;
  193. le le_inst0(
  194.     .ldclk(ldclk),
  195.     .ldi(serial_img5),
  196.     .ldo(serial_img6),
  197.     .lds(lds),
  198.  
  199.     .sysclk(sysclk0),
  200.     .in( {lut0_in0,lut0_in1,lut0_in2,lut0_in3} ),
  201.     .rena(rena0),
  202.     .rout(rout0),
  203.     .lout(lout0),
  204.     .pout(out_pin[0])
  205. );
  206.  
  207. // Logic Element #1 and connections
  208.  
  209. //multiplexer for LE1 clk: can select from 3 regs output or system clock
  210. wire serial_img7;
  211. wire sysclk1;
  212. pmux4 pmux_inst_clk1(
  213.     .ldclk(ldclk),
  214.     .ldi(serial_img6),
  215.     .ldo(serial_img7),
  216.     .lds(lds),
  217.     .in( { rout0, clk, rout2, rout3} ),
  218.     .out(sysclk1)
  219.     );
  220.  
  221. wire serial_img8;
  222. wire rena1;
  223. pmux8 pmux_inst_ena1(
  224.     .ldclk(ldclk),
  225.     .ldi(serial_img7),
  226.     .ldo(serial_img8),
  227.     .lds(lds),
  228.     .in( {lout0, in_pin[1], lout2, lout3, rout0, 1'b1, rout2, rout3} ),
  229.     .out(rena1)
  230.     );
  231.  
  232. wire serial_img9;
  233. wire lut1_in0;
  234. pmux8 pmux_inst_lut10(
  235.     .ldclk(ldclk),
  236.     .ldi(serial_img8),
  237.     .ldo(serial_img9),
  238.     .lds(lds),
  239.     .in( { lout0, in_pin[0], lout2, lout3, rout0, rout1, rout2, rout3} ),
  240.     .out(lut1_in0)
  241.     );
  242.  
  243. wire serial_img10;
  244. wire lut1_in1;
  245. pmux8 pmux_inst_lut11(
  246.     .ldclk(ldclk),
  247.     .ldi(serial_img9),
  248.     .ldo(serial_img10),
  249.     .lds(lds),
  250.     .in( { lout0, in_pin[1], lout2, lout3, rout0, rout1, rout2, rout3} ),
  251.     .out(lut1_in1)
  252.     );
  253.  
  254. wire serial_img11;
  255. wire lut1_in2;
  256. pmux8 pmux_inst_lut12(
  257.     .ldclk(ldclk),
  258.     .ldi(serial_img10),
  259.     .ldo(serial_img11),
  260.     .lds(lds),
  261.     .in( { lout0, in_pin[2], lout2, lout3, rout0, rout1, rout2, rout3} ),
  262.     .out(lut1_in2)
  263.     );
  264.  
  265. wire serial_img12;
  266. wire lut1_in3;
  267. pmux8 pmux_inst_lut13(
  268.     .ldclk(ldclk),
  269.     .ldi(serial_img11),
  270.     .ldo(serial_img12),
  271.     .lds(lds),
  272.     .in( { lout0, in_pin[3], lout2, lout3, rout0, rout1, rout2, rout3} ),
  273.     .out(lut1_in3)
  274.     );
  275.  
  276. wire serial_img13;
  277. wire rout1, lout1;
  278. le le_inst1(
  279.     .ldclk(ldclk),
  280.     .ldi(serial_img12),
  281.     .ldo(serial_img13),
  282.     .lds(lds),
  283.  
  284.     .sysclk(sysclk1),
  285.     .in( {lut1_in0,lut1_in1,lut1_in2,lut1_in3} ),
  286.     .rena(rena1),
  287.     .rout(rout1),
  288.     .lout(lout1),
  289.     .pout(out_pin[1])
  290. );
  291.  
  292. // Logic Element #2 and connections
  293.  
  294. //multiplexer for LE2 clk: can select from 3 regs output or system clock
  295. wire serial_img14;
  296. wire sysclk2;
  297. pmux4 pmux_inst_clk2(
  298.     .ldclk(ldclk),
  299.     .ldi(serial_img13),
  300.     .ldo(serial_img14),
  301.     .lds(lds),
  302.     .in( { rout0, rout1, clk, rout3} ),
  303.     .out(sysclk2)
  304.     );
  305.  
  306. wire serial_img15;
  307. wire rena2;
  308. pmux8 pmux_inst_ena2(
  309.     .ldclk(ldclk),
  310.     .ldi(serial_img14),
  311.     .ldo(serial_img15),
  312.     .lds(lds),
  313.     .in( {lout0, lout1, in_pin[2], lout3, rout0, rout1, 1'b1, rout3} ),
  314.     .out(rena2)
  315.     );
  316.  
  317. wire serial_img16;
  318. wire lut2_in0;
  319. pmux8 pmux_inst_lut20(
  320.     .ldclk(ldclk),
  321.     .ldi(serial_img15),
  322.     .ldo(serial_img16),
  323.     .lds(lds),
  324.     .in( { lout0, lout1, in_pin[0], lout3, rout0, rout1, rout2, rout3} ),
  325.     .out(lut2_in0)
  326.     );
  327.  
  328. wire serial_img17;
  329. wire lut2_in1;
  330. pmux8 pmux_inst_lut21(
  331.     .ldclk(ldclk),
  332.     .ldi(serial_img16),
  333.     .ldo(serial_img17),
  334.     .lds(lds),
  335.     .in( { lout0, lout1, in_pin[1], lout3, rout0, rout1, rout2, rout3} ),
  336.     .out(lut2_in1)
  337.     );
  338.  
  339. wire serial_img18;
  340. wire lut2_in2;
  341. pmux8 pmux_inst_lut22(
  342.     .ldclk(ldclk),
  343.     .ldi(serial_img17),
  344.     .ldo(serial_img18),
  345.     .lds(lds),
  346.     .in( { lout0, lout1, in_pin[2], lout3, rout0, rout1, rout2, rout3} ),
  347.     .out(lut2_in2)
  348.     );
  349.  
  350. wire serial_img19;
  351. wire lut2_in3;
  352. pmux8 pmux_inst_lut23(
  353.     .ldclk(ldclk),
  354.     .ldi(serial_img18),
  355.     .ldo(serial_img19),
  356.     .lds(lds),
  357.     .in( { lout0, lout1, in_pin[3], lout3, rout0, rout1, rout2, rout3} ),
  358.     .out(lut2_in3)
  359.     );
  360.  
  361. wire serial_img20;
  362. wire rout2, lout2;
  363. le le_inst2(
  364.     .ldclk(ldclk),
  365.     .ldi(serial_img19),
  366.     .ldo(serial_img20),
  367.     .lds(lds),
  368.  
  369.     .sysclk(sysclk2),
  370.     .in( {lut2_in0,lut2_in1,lut2_in2,lut2_in3} ),
  371.     .rena(rena2),
  372.     .rout(rout2),
  373.     .lout(lout2),
  374.     .pout(out_pin[2])
  375. );
  376.  
  377. // Logic Element #3 and connections
  378.  
  379. //multiplexer for LE3 clk: can select from 3 regs output or system clock
  380. wire serial_img21;
  381. wire sysclk3;
  382. pmux4 pmux_inst_clk3(
  383.     .ldclk(ldclk),
  384.     .ldi(serial_img20),
  385.     .ldo(serial_img21),
  386.     .lds(lds),
  387.     .in( { rout0, rout1, rout2, clk} ),
  388.     .out(sysclk3)
  389.     );
  390.  
  391. wire serial_img22;
  392. wire rena3;
  393. pmux8 pmux_inst_ena3(
  394.     .ldclk(ldclk),
  395.     .ldi(serial_img21),
  396.     .ldo(serial_img22),
  397.     .lds(lds),
  398.     .in( {lout0, lout1, lout2, in_pin[3], rout0, rout1, rout2, 1'b1} ),
  399.     .out(rena3)
  400.     );
  401.  
  402. wire serial_img23;
  403. wire lut3_in0;
  404. pmux8 pmux_inst_lut30(
  405.     .ldclk(ldclk),
  406.     .ldi(serial_img22),
  407.     .ldo(serial_img23),
  408.     .lds(lds),
  409.     .in( { lout0, lout1, lout2, in_pin[0], rout0, rout1, rout2, rout3} ),
  410.     .out(lut3_in0)
  411.     );
  412.  
  413. wire serial_img24;
  414. wire lut3_in1;
  415. pmux8 pmux_inst_lut31(
  416.     .ldclk(ldclk),
  417.     .ldi(serial_img23),
  418.     .ldo(serial_img24),
  419.     .lds(lds),
  420.     .in( { lout0, lout1, lout2, in_pin[0], rout0, rout1, rout2, rout3} ),
  421.     .out(lut3_in1)
  422.     );
  423.  
  424. wire serial_img25;
  425. wire lut3_in2;
  426. pmux8 pmux_inst_lut32(
  427.     .ldclk(ldclk),
  428.     .ldi(serial_img24),
  429.     .ldo(serial_img25),
  430.     .lds(lds),
  431.     .in( { lout0, lout1, lout2, in_pin[0], rout0, rout1, rout2, rout3} ),
  432.     .out(lut3_in2)
  433.     );
  434.  
  435. wire serial_img26;
  436. wire lut3_in3;
  437. pmux8 pmux_inst_lut33(
  438.     .ldclk(ldclk),
  439.     .ldi(serial_img25),
  440.     .ldo(serial_img26),
  441.     .lds(lds),
  442.     .in( { lout0, lout1, lout2, in_pin[0], rout0, rout1, rout2, rout3} ),
  443.     .out(lut3_in3)
  444.     );
  445.  
  446. wire serial_img27;
  447. wire rout3, lout3;
  448. le le_inst3(
  449.     .ldclk(ldclk),
  450.     .ldi(serial_img26),
  451.     .ldo(serial_img27),
  452.     .lds(lds),
  453.  
  454.     .sysclk(sysclk3),
  455.     .in( {lut3_in0,lut3_in1,lut3_in2,lut3_in3} ),
  456.     .rena(rena3),
  457.     .rout(rout3),
  458.     .lout(lout3),
  459.     .pout(out_pin[3])
  460. );
  461.  
  462. always @(posedge ldclk)
  463.     if(lds)
  464.         ldo <= serial_img27;
  465.  
  466. endmodule
  467.  

facebook  GitHub  YouTube  Twitter
Вы здесь: Начало Проекты Примеры программ Исходный код ПЛИС внутри ПЛИС