Исходный код тестбенча для мПЛИС (проект ПЛИС внутри ПЛИС)

  1.  
  2. //testbench for mini_cpld
  3.  
  4. module test;
  5.  
  6. //64 bytes array used for cpld image
  7. reg [7:0] value[0:63];
  8. integer i,j,a,b,c;
  9.  
  10. //signals used to load mini_cpld
  11. reg ldclk,ldi,lds;
  12. wire ldo;
  13.  
  14. reg clk;
  15.  
  16. //input pins of mini_cpld
  17. reg [3:0]ipin;
  18.  
  19. //output pins of mini_cpld
  20. wire out_pin0;
  21. wire out_pin1;
  22. wire out_pin2;
  23. wire out_pin3;
  24.  
  25. //instance of mini_cpld being tested
  26. mini_cpld mini_cpld_inst(
  27.     .ldclk(ldclk),
  28.     .ldi(ldi),
  29.     .ldo(ldo),
  30.     .lds(lds),
  31.  
  32.     .clk(clk),
  33.     .in_pin(ipin),
  34.     .out_pin( {out_pin3,out_pin2,out_pin1,out_pin0} )
  35. );
  36.  
  37. reg [3:0]num_bits;
  38. reg [3:0]val;
  39.  
  40. initial
  41. begin
  42.     //load "cpld image" into temprorary array
  43.     $readmemb("image_shift.dat",value);
  44.     $display("mini_cpld image file");
  45.     for(i=0; i<64; i=i+1)
  46.         $display("%d %b",i,value[i]);
  47.  
  48.     //create MIF file used by real Quartus II project for UFM init
  49.     make_mif();
  50.  
  51.     //start with zeros
  52.     ldclk=0;
  53.     clk=0;
  54.     ldi=0;
  55.     lds=0;
  56.     ipin=0;
  57.  
  58.     @(posedge ldclk);
  59.     lds=1;
  60.  
  61.     //load image into cpld
  62.     i=0;
  63.     //low 4 bits mean loadable value
  64.     val = value[i] & 4'hF;
  65.     //high 4 bits mean number of bits to load
  66.     num_bits = value[i] >> 4;
  67.     while(num_bits != 0)
  68.     begin
  69.         //$display("load %d %4b %4b",i,num_bits,val);
  70.         sendbits();
  71.         i=i+1;
  72.         val = value[i] & 4'hF;
  73.         num_bits = value[i] >> 4;
  74.     end
  75.     lds=0;
  76.    
  77.     $display("load finished");
  78.  
  79.     //simulate single input pin change
  80.     ipin[1]=1;
  81.     #30;
  82.     ipin[1]=0;
  83.     #35;
  84.     ipin[1]=1;
  85.     #50;
  86.     ipin[1]=0;
  87.     #70;
  88.     ipin[1]=1;
  89.     #30;
  90.     ipin[1]=0;
  91.     #10000;
  92.     $finish;
  93. end
  94.  
  95. //task used to load several bits into mini_cpld
  96. task sendbits;
  97. begin
  98.     for(j=0; j<num_bits; j=j+1)
  99.     begin
  100.         ldi = val[3];
  101.         @(posedge ldclk)
  102.         #0;
  103.         val = val << 1;
  104.     end
  105. end
  106. endtask
  107.  
  108. //generate Memory Initialization File (MIF) for
  109. //Altera MAX II CPLD User Flash Memory (UFM)
  110. integer acc;
  111. integer acc_num_bits;
  112. task make_mif;
  113. begin
  114.     $display("-------------------------");
  115.     $display("WIDTH = 16;");
  116.     $display("DEPTH = 512;");
  117.     $display("ADDRESS_RADIX = HEX;");
  118.     $display("DATA_RADIX = HEX;");
  119.     $display("CONTENT BEGIN");
  120.     $display("  00000000 : 00000000;");
  121.     $display("  00000001 : 00000000;");
  122.     $display("  00000002 : 00000000;");
  123.     $display("  00000003 : 00000000;");
  124.     a=4;    //next addr to emit
  125.     c=1;    //cycle flag
  126.     i=0;    //index of word in image memory
  127.     acc = 0;
  128.     acc_num_bits=0;
  129.     num_bits = 1;
  130.     while( (num_bits > 0) && (a<32) )
  131.     begin
  132.         //get word from memory
  133.         num_bits = value[i] >> 4;
  134.         val = (value[i] & 4'hF) >> (4-num_bits);
  135.         i=i+1;
  136.         //put bits into accumulator
  137.         acc = acc << num_bits;
  138.         acc = acc | val;
  139.         acc_num_bits = acc_num_bits + num_bits;
  140.         //$display(">%X %d;",acc,acc_num_bits);
  141.         if(acc_num_bits>15)
  142.         begin
  143.             b=acc>>(acc_num_bits-16);
  144.             $display("  %X : %X;",a,b & 16'hFFFF);
  145.             acc_num_bits = acc_num_bits-16;
  146.             a=a+1;
  147.         end
  148.     end
  149.     if(acc_num_bits>0)
  150.     begin
  151.         b=acc<<(16-acc_num_bits);
  152.         $display("  %X : %X;",a,b & 16'hFFFF);
  153.         a=a+1;
  154.     end
  155.     $display("  %X : %X;",a,0);
  156.     $display("END");
  157.     $display("-------------------------");
  158. end
  159. endtask
  160.  
  161. //generate clock signal for image loading into mini_cpld
  162. always
  163. begin
  164.     #5 ldclk = ~ldclk;
  165. end
  166.  
  167. //generate system clock signal
  168. always
  169. begin
  170.     #10 clk = ~clk;
  171. end
  172.  
  173. initial
  174. begin
  175.     $dumpfile("out.vcd");
  176.     $dumpvars(0,test);
  177. end
  178.  
  179. endmodule
  180.