Существует такой интересный проект OSS CAD Suite. Это пакет программ с открытым исходным кодом для разработки цифровой логики FPGA. Пакет поддерживает несколько типов FPGA микросхем, в основном Lattice (ice40, ecp5, machxo2, nexus), но так же и некоторые микросхемы Gowin.
В этой статье я расскажу, как компилировать проекты для нашей платы Марсоход3GW с помощью OSS CAD Suite. Многие проекты получится компилировать, но, к сожалению не все. Разработчики пакета не имеют полной документации на микросхемы Gowin и это ограничивает их возможности. Каждый желающий может присоединиться к этой open source разработке и внести свой вклад. Более того, CAD поддерживает FPGA типа generic, то есть абстрактные FPGA, которых не существует. Можно проектировать свою ПЛИС и адаптировать это ПО для сборки проектов для вашей FPGA микросхемы.
Расскажу, как использовать OSS CAD Suite для проектирования под нашу плату Marsohod3GW в среде ОС Windows.
Итак, приступим.
1. Скачиваем пакет программ OSS CAD Suite. На странице гихаб https://github.com/YosysHQ/oss-cad-suite-build есть кнопки с выбором используемой платформы. Например, выбираем "windows-x64/passing". Переходим поссылке, выбираем oss-cad-suite-windows-x64-20230508.exe и скачиваем.
2. Переносим полученный файл в папку, которая дальше будет нашей рабочей папкой. Мой совет, от греха подальше, имя папки не должно содержать пробелы и русские буквы.
3. Запускаем exe файл и он распаковывает всё ПО прямо здесь.
4. Запускаем в Windows консоль CMD.EXE. Переходим в нашу папку, где расположен распакованный OSS CAD Suite. Запускаем environment.bat. Этот скрипт создает рабочее окружение для всего пакета програм CAD.
5. Теперь в этой же консоли переходим в папку с нашим проектом для платы Марсоход3GW. Я для пробы хочу скомпилировать проект _clk_pll_counter. Поэтому перехожу в эту папку: [OSS CAD Suite] D:\Gowin\oss-cad-suite>cd cd ..\Marsohod3GW\_clk_pll_counter\src
Этот проект интересен тем, что в нём используется проприетарный компонент Gowin rPLL. Посмотрим, как он синтезируется и размещается в FPGA, возьмёт ли его CAD Suite?
6. Для сборки проекта нам нужно выполнить три последовательные шага:
- синтез (конвертация проекта из языка высокого уровня Verilog HDL в представление в виде примитивов, гейтов, триггеров и т.д)
- размещение и трассировка логики в ПЛИС
- создание битстрима готового для загрузки в ПЛИС.
В OSS CAD Suite для этих целей есть три программы: yosys, nextpnr-gowin и gowin_pack. Ниже рассмотрим эти этапы подробнее.
7. Создаю папку output, где будет храниться полученный результат.
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>mkdir output
8. Запускаю команду для синтеза (результат синтеза будет в файле outut/out-synth.json):
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>yosys -p "read_verilog top.v gowin_rpll/gowin_rpll.v; synth_gowin -json output/out-synth.json"
[OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>yosys -p "read_verilog top.v gowin_rpll/gowin_rpll.v; synth_gowin -json output/out-synth.json"
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <Этот адрес электронной почты защищён от спам-ботов. У вас должен быть включен JavaScript для просмотра.> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.28+6 (git sha1 cee3cb31b, x86_64-w64-mingw32-g++ 9.2.1 -Os)
-- Running command `read_verilog top.v gowin_rpll/gowin_rpll.v; synth_gowin -json output/out-synth.json' --
1. Executing Verilog-2005 frontend: top.v
Parsing Verilog input from `top.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: gowin_rpll/gowin_rpll.v
Parsing Verilog input from `gowin_rpll/gowin_rpll.v' to AST representation.
Generating RTLIL representation for module `\Gowin_rPLL'.
Successfully finished Verilog frontend.
3. Executing SYNTH_GOWIN pass.
3.1. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\__APICULA_LUT5'.
Generating RTLIL representation for module `\__APICULA_LUT6'.
Generating RTLIL representation for module `\__APICULA_LUT7'.
Generating RTLIL representation for module `\__APICULA_LUT8'.
Generating RTLIL representation for module `\MUX2'.
Generating RTLIL representation for module `\MUX2_LUT5'.
Generating RTLIL representation for module `\MUX2_LUT6'.
Generating RTLIL representation for module `\MUX2_LUT7'.
Generating RTLIL representation for module `\MUX2_LUT8'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFE'.
Generating RTLIL representation for module `\DFFS'.
Generating RTLIL representation for module `\DFFSE'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\DFFRE'.
Generating RTLIL representation for module `\DFFP'.
Generating RTLIL representation for module `\DFFPE'.
Generating RTLIL representation for module `\DFFC'.
Generating RTLIL representation for module `\DFFCE'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFNE'.
Generating RTLIL representation for module `\DFFNS'.
Generating RTLIL representation for module `\DFFNSE'.
Generating RTLIL representation for module `\DFFNR'.
Generating RTLIL representation for module `\DFFNRE'.
Generating RTLIL representation for module `\DFFNP'.
Generating RTLIL representation for module `\DFFNPE'.
Generating RTLIL representation for module `\DFFNC'.
Generating RTLIL representation for module `\DFFNCE'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\TBUF'.
Generating RTLIL representation for module `\IOBUF'.
Generating RTLIL representation for module `\ELVDS_OBUF'.
Generating RTLIL representation for module `\TLVDS_OBUF'.
Generating RTLIL representation for module `\OSER4'.
Generating RTLIL representation for module `\OSER8'.
Generating RTLIL representation for module `\OSER10'.
Generating RTLIL representation for module `\OVIDEO'.
Generating RTLIL representation for module `\OSER16'.
Generating RTLIL representation for module `\IDES4'.
Generating RTLIL representation for module `\IDES8'.
Generating RTLIL representation for module `\IDES10'.
Generating RTLIL representation for module `\IVIDEO'.
Generating RTLIL representation for module `\IDES16'.
Generating RTLIL representation for module `\IDDR'.
Generating RTLIL representation for module `\IDDRC'.
Generating RTLIL representation for module `\ODDR'.
Generating RTLIL representation for module `\ODDRC'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S1'.
Generating RTLIL representation for module `\RAM16S2'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\RAM16SDP1'.
Generating RTLIL representation for module `\RAM16SDP2'.
Generating RTLIL representation for module `\RAM16SDP4'.
Generating RTLIL representation for module `\SP'.
Generating RTLIL representation for module `\SPX9'.
Generating RTLIL representation for module `\SDP'.
Generating RTLIL representation for module `\SDPX9'.
Generating RTLIL representation for module `\DP'.
Generating RTLIL representation for module `\DPX9'.
Generating RTLIL representation for module `\rPLL'.
Generating RTLIL representation for module `\PLLVR'.
Generating RTLIL representation for module `\OSC'.
Generating RTLIL representation for module `\OSCZ'.
Generating RTLIL representation for module `\OSCF'.
Generating RTLIL representation for module `\OSCH'.
Generating RTLIL representation for module `\OSCW'.
Generating RTLIL representation for module `\OSCO'.
Successfully finished Verilog frontend.
3.2. Executing HIERARCHY pass (managing design hierarchy).
3.2.1. Finding top of design hierarchy..
root of 1 design levels: Gowin_rPLL
root of 2 design levels: top
Automatically selected top as design top module.
3.2.2. Analyzing design hierarchy..
Top module: \top
Used module: \Gowin_rPLL
3.2.3. Analyzing design hierarchy..
Top module: \top
Used module: \Gowin_rPLL
Removed 0 unused modules.
3.3. Executing PROC pass (convert processes to netlists).
3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\ALU.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:913$233'.
Cleaned up 1 empty switch.
3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229 in module DFFNCE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:515$227 in module DFFNC.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225 in module DFFNPE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:476$223 in module DFFNP.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:457$221 in module DFFNRE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:437$219 in module DFFNR.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:418$217 in module DFFNSE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:398$215 in module DFFNS.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209 in module DFFCE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:328$207 in module DFFC.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205 in module DFFPE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:289$203 in module DFFP.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:270$201 in module DFFRE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:250$199 in module DFFR.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:231$197 in module DFFSE.
Marked 1 switch rules as full_case in process $proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:211$195 in module DFFS.
Removed a total of 0 dead cases.
3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 29 assignments to connections.
3.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$230'.
Set init value: \Q = 1'0
Found init rule in `\DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$228'.
Set init value: \Q = 1'0
Found init rule in `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$226'.
Set init value: \Q = 1'1
Found init rule in `\DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$224'.
Set init value: \Q = 1'1
Found init rule in `\DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$222'.
Set init value: \Q = 1'0
Found init rule in `\DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$220'.
Set init value: \Q = 1'0
Found init rule in `\DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$218'.
Set init value: \Q = 1'1
Found init rule in `\DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$216'.
Set init value: \Q = 1'1
Found init rule in `\DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$214'.
Set init value: \Q = 1'0
Found init rule in `\DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$212'.
Set init value: \Q = 1'0
Found init rule in `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$210'.
Set init value: \Q = 1'0
Found init rule in `\DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$208'.
Set init value: \Q = 1'0
Found init rule in `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$206'.
Set init value: \Q = 1'1
Found init rule in `\DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$204'.
Set init value: \Q = 1'1
Found init rule in `\DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$202'.
Set init value: \Q = 1'0
Found init rule in `\DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$200'.
Set init value: \Q = 1'0
Found init rule in `\DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$198'.
Set init value: \Q = 1'1
Found init rule in `\DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$196'.
Set init value: \Q = 1'1
Found init rule in `\DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$194'.
Set init value: \Q = 1'0
Found init rule in `\DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$192'.
Set init value: \Q = 1'0
Found init rule in `\top.$proc$top.v:28$7'.
Set init value: \cnt = 29'00000000000000000000000000000
3.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \CLEAR in `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229'.
Found async reset \CLEAR in `\DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:515$227'.
Found async reset \PRESET in `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225'.
Found async reset \PRESET in `\DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:476$223'.
Found async reset \CLEAR in `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209'.
Found async reset \CLEAR in `\DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:328$207'.
Found async reset \PRESET in `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205'.
Found async reset \PRESET in `\DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:289$203'.
3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ALU.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:913$233'.
Creating decoders for process `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$230'.
Creating decoders for process `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$228'.
Creating decoders for process `\DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:515$227'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$226'.
Creating decoders for process `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$224'.
Creating decoders for process `\DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:476$223'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$222'.
Creating decoders for process `\DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:457$221'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$220'.
Creating decoders for process `\DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:437$219'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$218'.
Creating decoders for process `\DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:418$217'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$216'.
Creating decoders for process `\DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:398$215'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$214'.
Creating decoders for process `\DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:381$213'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$212'.
Creating decoders for process `\DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:366$211'.
Creating decoders for process `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$210'.
Creating decoders for process `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$208'.
Creating decoders for process `\DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:328$207'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$206'.
Creating decoders for process `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$204'.
Creating decoders for process `\DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:289$203'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$202'.
Creating decoders for process `\DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:270$201'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$200'.
Creating decoders for process `\DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:250$199'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$198'.
Creating decoders for process `\DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:231$197'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$196'.
Creating decoders for process `\DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:211$195'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$194'.
Creating decoders for process `\DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:194$193'.
1/1: $0\Q[0:0]
Creating decoders for process `\DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$192'.
Creating decoders for process `\DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:179$191'.
Creating decoders for process `\top.$proc$top.v:28$7'.
Creating decoders for process `\top.$proc$top.v:30$1'.
3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ALU.\C' using process `\ALU.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:913$233'.
created direct connection (no actual register cell created).
Creating register for signal `\ALU.\S' using process `\ALU.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:913$233'.
created direct connection (no actual register cell created).
Creating register for signal `\DFFNCE.\Q' using process `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229'.
created $adff cell `$procdff$321' with negative edge clock and positive level reset.
Creating register for signal `\DFFNC.\Q' using process `\DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:515$227'.
created $adff cell `$procdff$322' with negative edge clock and positive level reset.
Creating register for signal `\DFFNPE.\Q' using process `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225'.
created $adff cell `$procdff$323' with negative edge clock and positive level reset.
Creating register for signal `\DFFNP.\Q' using process `\DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:476$223'.
created $adff cell `$procdff$324' with negative edge clock and positive level reset.
Creating register for signal `\DFFNRE.\Q' using process `\DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:457$221'.
created $dff cell `$procdff$325' with negative edge clock.
Creating register for signal `\DFFNR.\Q' using process `\DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:437$219'.
created $dff cell `$procdff$326' with negative edge clock.
Creating register for signal `\DFFNSE.\Q' using process `\DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:418$217'.
created $dff cell `$procdff$327' with negative edge clock.
Creating register for signal `\DFFNS.\Q' using process `\DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:398$215'.
created $dff cell `$procdff$328' with negative edge clock.
Creating register for signal `\DFFNE.\Q' using process `\DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:381$213'.
created $dff cell `$procdff$329' with negative edge clock.
Creating register for signal `\DFFN.\Q' using process `\DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:366$211'.
created $dff cell `$procdff$330' with negative edge clock.
Creating register for signal `\DFFCE.\Q' using process `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209'.
created $adff cell `$procdff$331' with positive edge clock and positive level reset.
Creating register for signal `\DFFC.\Q' using process `\DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:328$207'.
created $adff cell `$procdff$332' with positive edge clock and positive level reset.
Creating register for signal `\DFFPE.\Q' using process `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205'.
created $adff cell `$procdff$333' with positive edge clock and positive level reset.
Creating register for signal `\DFFP.\Q' using process `\DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:289$203'.
created $adff cell `$procdff$334' with positive edge clock and positive level reset.
Creating register for signal `\DFFRE.\Q' using process `\DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:270$201'.
created $dff cell `$procdff$335' with positive edge clock.
Creating register for signal `\DFFR.\Q' using process `\DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:250$199'.
created $dff cell `$procdff$336' with positive edge clock.
Creating register for signal `\DFFSE.\Q' using process `\DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:231$197'.
created $dff cell `$procdff$337' with positive edge clock.
Creating register for signal `\DFFS.\Q' using process `\DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:211$195'.
created $dff cell `$procdff$338' with positive edge clock.
Creating register for signal `\DFFE.\Q' using process `\DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:194$193'.
created $dff cell `$procdff$339' with positive edge clock.
Creating register for signal `\DFF.\Q' using process `\DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:179$191'.
created $dff cell `$procdff$340' with positive edge clock.
Creating register for signal `\top.\cnt' using process `\top.$proc$top.v:30$1'.
created $dff cell `$procdff$341' with positive edge clock.
Creating register for signal `\top.\moving_bit' using process `\top.$proc$top.v:30$1'.
created $dff cell `$procdff$342' with positive edge clock.
3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `ALU.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:913$233'.
Removing empty process `DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$230'.
Found and cleaned up 1 empty switch in `\DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229'.
Removing empty process `DFFNCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:535$229'.
Removing empty process `DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$228'.
Removing empty process `DFFNC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:515$227'.
Removing empty process `DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$226'.
Found and cleaned up 1 empty switch in `\DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225'.
Removing empty process `DFFNPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:496$225'.
Removing empty process `DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$224'.
Removing empty process `DFFNP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:476$223'.
Removing empty process `DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$222'.
Found and cleaned up 2 empty switches in `\DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:457$221'.
Removing empty process `DFFNRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:457$221'.
Removing empty process `DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$220'.
Found and cleaned up 1 empty switch in `\DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:437$219'.
Removing empty process `DFFNR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:437$219'.
Removing empty process `DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$218'.
Found and cleaned up 2 empty switches in `\DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:418$217'.
Removing empty process `DFFNSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:418$217'.
Removing empty process `DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$216'.
Found and cleaned up 1 empty switch in `\DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:398$215'.
Removing empty process `DFFNS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:398$215'.
Removing empty process `DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$214'.
Found and cleaned up 1 empty switch in `\DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:381$213'.
Removing empty process `DFFNE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:381$213'.
Removing empty process `DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$212'.
Removing empty process `DFFN.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:366$211'.
Removing empty process `DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$210'.
Found and cleaned up 1 empty switch in `\DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209'.
Removing empty process `DFFCE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:348$209'.
Removing empty process `DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$208'.
Removing empty process `DFFC.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:328$207'.
Removing empty process `DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$206'.
Found and cleaned up 1 empty switch in `\DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205'.
Removing empty process `DFFPE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:309$205'.
Removing empty process `DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$204'.
Removing empty process `DFFP.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:289$203'.
Removing empty process `DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$202'.
Found and cleaned up 2 empty switches in `\DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:270$201'.
Removing empty process `DFFRE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:270$201'.
Removing empty process `DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$200'.
Found and cleaned up 1 empty switch in `\DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:250$199'.
Removing empty process `DFFR.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:250$199'.
Removing empty process `DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$198'.
Found and cleaned up 2 empty switches in `\DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:231$197'.
Removing empty process `DFFSE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:231$197'.
Removing empty process `DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$196'.
Found and cleaned up 1 empty switch in `\DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:211$195'.
Removing empty process `DFFS.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:211$195'.
Removing empty process `DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$194'.
Found and cleaned up 1 empty switch in `\DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:194$193'.
Removing empty process `DFFE.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:194$193'.
Removing empty process `DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:0$192'.
Removing empty process `DFF.$proc$D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_sim.v:179$191'.
Removing empty process `top.$proc$top.v:28$7'.
Removing empty process `top.$proc$top.v:30$1'.
Cleaned up 18 empty switches.
3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module Gowin_rPLL.
Optimizing module top.
3.4. Executing FLATTEN pass (flatten design).
Deleting now unused module Gowin_rPLL.
3.5. Executing TRIBUF pass.
3.6. Executing DEMINOUT pass (demote inout ports to input or output).
3.7. Executing SYNTH pass.
3.7.1. Executing PROC pass (convert processes to netlists).
3.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
3.7.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
3.7.1.4. Executing PROC_INIT pass (extract init attributes).
3.7.1.5. Executing PROC_ARST pass (detect async resets in processes).
3.7.1.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
3.7.1.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
3.7.1.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.7.1.9. Executing PROC_DFF pass (convert process syncs to FFs).
3.7.1.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.7.1.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.7.1.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
3.7.4. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
3.7.5. Executing OPT pass (performing simple optimizations).
3.7.5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
3.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.5.6. Executing OPT_DFF pass (perform DFF optimizations).
3.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.5.9. Finished OPT passes. (There is nothing left to do.)
3.7.6. Executing FSM pass (extract and optimize FSM).
3.7.6.1. Executing FSM_DETECT pass (finding FSMs in design).
3.7.6.2. Executing FSM_EXTRACT pass (extracting FSM from design).
3.7.6.3. Executing FSM_OPT pass (simple optimizations of FSMs).
3.7.6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.6.5. Executing FSM_OPT pass (simple optimizations of FSMs).
3.7.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
3.7.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
3.7.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
3.7.7. Executing OPT pass (performing simple optimizations).
3.7.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
3.7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.7.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.7.6. Executing OPT_DFF pass (perform DFF optimizations).
3.7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.7.9. Finished OPT passes. (There is nothing left to do.)
3.7.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell top.$add$top.v:32$2 ($add).
Removed top 3 bits (of 32) from port Y of cell top.$add$top.v:32$2 ($add).
Removed top 7 bits (of 8) from port A of cell top.$shl$top.v:34$3 ($shl).
3.7.9. Executing PEEPOPT pass (run peephole optimizers).
3.7.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
3.7.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $add$top.v:32$2 ($add).
creating $alu model for $macc $add$top.v:32$2.
creating $alu cell for $add$top.v:32$2: $auto$alumacc.cc:485:replace_alu$343
created 1 $alu and 0 $macc cells.
3.7.12. Executing SHARE pass (SAT-based resource sharing).
Found 2 cells in module top that may be considered for resource sharing.
Analyzing resource sharing options for $shr$top.v:35$4 ($shr):
Found 1 activation_patterns using ctrl signal \cnt [26].
No candidates found.
Analyzing resource sharing options for $shl$top.v:34$3 ($shl):
Found 1 activation_patterns using ctrl signal \cnt [26].
No candidates found.
3.7.13. Executing OPT pass (performing simple optimizations).
3.7.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
3.7.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.7.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.7.13.6. Executing OPT_DFF pass (perform DFF optimizations).
3.7.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.7.13.9. Finished OPT passes. (There is nothing left to do.)
3.7.14. Executing MEMORY pass.
3.7.14.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
3.7.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
3.7.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
3.7.14.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
3.7.14.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
3.7.14.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.14.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
3.7.14.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
3.7.14.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.7.14.10. Executing MEMORY_COLLECT pass (generating $mem cells).
3.7.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.8. Executing MEMORY_LIBMAP pass (mapping memories to cells).
3.9. Executing TECHMAP pass (map to technology primitives).
3.9.1. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/lutrams_map.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GOWIN_LUTRAM_'.
Successfully finished Verilog frontend.
3.9.2. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/brams_map.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GOWIN_SP_'.
Generating RTLIL representation for module `\$__GOWIN_DP_'.
Generating RTLIL representation for module `\$__GOWIN_SDP_'.
Successfully finished Verilog frontend.
3.9.3. Continuing TECHMAP pass.
No more expansions possible.
3.10. Executing OPT pass (performing simple optimizations).
3.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.10.3. Executing OPT_DFF pass (perform DFF optimizations).
3.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.10.5. Finished fast OPT passes.
3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
3.12. Executing OPT pass (performing simple optimizations).
3.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.12.6. Executing OPT_DFF pass (perform DFF optimizations).
3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.12.9. Finished OPT passes. (There is nothing left to do.)
3.13. Executing TECHMAP pass (map to technology primitives).
3.13.1. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/techmap.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
3.13.2. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/arith_map.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_gw1n_alu'.
Successfully finished Verilog frontend.
3.13.3. Continuing TECHMAP pass.
Using template $paramod$80fd49bc875a8a1ceaa5f1b164eef265e92f0909\_80_gw1n_alu for cells of type $alu.
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:201e743a7a42c7f70f2a0baf6d181f7abbbb0965$paramod$e02a20504e61ebe09eb52d686bcb6c2238e4a84f\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
3.14. Executing OPT pass (performing simple optimizations).
3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 13 cells.
3.14.3. Executing OPT_DFF pass (perform DFF optimizations).
3.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 57 unused wires.
3.14.5. Finished fast OPT passes.
3.15. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Mapping port top.ADC_CLK using OBUF.
Mapping port top.ADC_D using IBUF.
Mapping port top.CLK using IBUF.
Mapping port top.FTB0 using IBUF.
Mapping port top.FTB1 using OBUF.
Mapping port top.FTB2 using IBUF.
Mapping port top.FTB3 using OBUF.
Mapping port top.FTC using IBUF.
Mapping port top.FTD using IBUF.
Mapping port top.IO using OBUF.
Mapping port top.KEY0 using IBUF.
Mapping port top.KEY1 using IBUF.
Mapping port top.LED using OBUF.
Mapping port top.TMDS_CLK_N using OBUF.
Mapping port top.TMDS_CLK_P using OBUF.
Mapping port top.TMDS_D_N using OBUF.
Mapping port top.TMDS_D_P using OBUF.
3.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 9 unused wires.
3.17. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
3.18. Executing TECHMAP pass (map to technology primitives).
3.18.1. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_map.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
3.18.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
No more expansions possible.
3.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.20. Executing SIMPLEMAP pass (map simple cells to gate primitives).
3.21. Executing ABC pass (technology mapping using ABC).
3.21.1. Extracting gate netlist of module `\top' to `/input.blif'..
Extracted 29 gates and 47 wires to a netlist network with 17 inputs and 16 outputs.
3.21.1.1. Executing ABC.
Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC:
ABC: + read_blif /input.blif
ABC: + read_lut /lutdefs.txt
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + write_blif /output.blif
3.21.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 16
ABC RESULTS: internal signals: 14
ABC RESULTS: input signals: 17
ABC RESULTS: output signals: 16
Removing temp directory.
Removed 0 unused cells and 177 unused wires.
3.22. Executing TECHMAP pass (map to technology primitives).
3.22.1. Executing Verilog-2005 frontend: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_map.v
Parsing Verilog input from `D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
3.22.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$7d45bd12c01d1778446c9474bd2c34ae7ad041ca\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$92ae337dcfbfd75c23b894780eb529dcdde84bb2\$lut for cells of type $lut.
Using template $paramod$0a14d5e896aa3d4771d458c7bcc847abb47d8244\$lut for cells of type $lut.
Using template $paramod$c82d7aa204724568255de10e493596086641f722\$lut for cells of type $lut.
No more expansions possible.
3.23. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
3.24. Executing SETUNDEF pass (replace undef values with defined constants).
3.25. Executing HILOMAP pass (mapping to constant drivers).
Removed 0 unused cells and 33 unused wires.
3.26. Executing AUTONAME pass.
Renamed 447 objects in module top (10 iterations).
3.27. Executing HIERARCHY pass (managing design hierarchy).
3.27.1. Analyzing design hierarchy..
Top module: \top
3.27.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
3.28. Printing statistics.
=== top ===
Number of wires: 48
Number of wire bits: 247
Number of public wires: 48
Number of public wire bits: 247
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 152
ALU 29
DFF 37
GND 1
IBUF 29
LUT3 8
LUT4 8
OBUF 38
VCC 1
rPLL 1
3.29. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.
3.30. Executing JSON backend.
End of script. Logfile hash: 4e14c0eae6
Yosys 0.28+6 (git sha1 cee3cb31b, x86_64-w64-mingw32-g++ 9.2.1 -Os)
Time spent: 1% 18x opt_expr (0 sec), 1% 13x opt_clean (0 sec), ...
[OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>
Обратите внимание, в конце длинного лога программы есть сообщение "Found and reported 0 problems." Значит ошибок компиляции нет. Так же чуть выше есть отчёт об используемых ресурсах: типа ALU 29 штука, DFF 37 штук, rPLL 1 штука, и другие ресурсы.
9. Запускаю размещение и трассировку, Place & Route:
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>nextpnr-gowin --json output\out-synth.json --write output\out-pnr.json --device GW1NR-UV9QN88C6/I5 --cst board.cst
[OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>nextpnr-gowin --json output\out-synth.json --write output\out-pnr.json --device GW1NR-UV9QN88C6/I5 --cst board.cst Info: Series:GW1N-9 Device:GW1NR-9 Package:QFN88 Speed:C6/I5 Info: Packing constants.. Info: Packing Shadow RAM.. Info: Packing GSR.. Info: Packing IOs.. Info: Packing diff IOs.. Info: Packing IO logic.. Info: Packing wide LUTs.. Info: Packing LUT5s.. Info: Packing LUT6s.. Info: Packing LUT7s.. Info: Packing LUT8s.. Info: Packing ALUs.. Info: Packing LUT-FFs.. Info: Packing non-LUT FFs.. Info: Packing PLLs.. Info: Checksum: 0x3cde84c5 Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0x3cde84c5 Info: Device utilisation: Info: VCC: 1/ 1 100% Info: SLICE: 75/ 8640 0% Info: IOB: 67/ 274 24% Info: OSER16: 0/ 38 0% Info: IDES16: 0/ 38 0% Info: IOLOGIC: 0/ 296 0% Info: MUX2_LUT5: 0/ 4320 0% Info: MUX2_LUT6: 0/ 2160 0% Info: MUX2_LUT7: 0/ 1080 0% Info: MUX2_LUT8: 0/ 1056 0% Info: GND: 1/ 1 100% Info: RAMW: 0/ 270 0% Info: GSR: 1/ 1 100% Info: OSC: 0/ 1 0% Info: rPLL: 1/ 2 50% Info: Placed 67 cells based on constraints. Info: Creating initial analytic placement for 50 cells, random placement wirelen = 2099. Info: at initial placer iter 0, wirelen = 218 Info: at initial placer iter 1, wirelen = 172 Info: at initial placer iter 2, wirelen = 170 Info: at initial placer iter 3, wirelen = 171 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type rPLL: wirelen solved = 171, spread = 171, legal = 214; time = 0.00s Info: at iteration #1, type SLICE: wirelen solved = 216, spread = 243, legal = 313; time = 0.00s Info: at iteration #1, type VCC: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #1, type GND: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #1, type GSR: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #1, type ALL: wirelen solved = 175, spread = 308, legal = 365; time = 0.00s Info: at iteration #2, type rPLL: wirelen solved = 311, spread = 311, legal = 365; time = 0.00s Info: at iteration #2, type SLICE: wirelen solved = 225, spread = 305, legal = 311; time = 0.00s Info: at iteration #2, type VCC: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #2, type GND: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #2, type GSR: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #2, type ALL: wirelen solved = 172, spread = 245, legal = 306; time = 0.00s Info: at iteration #3, type rPLL: wirelen solved = 252, spread = 252, legal = 306; time = 0.00s Info: at iteration #3, type SLICE: wirelen solved = 229, spread = 318, legal = 324; time = 0.00s Info: at iteration #3, type VCC: wirelen solved = 324, spread = 324, legal = 324; time = 0.00s Info: at iteration #3, type GND: wirelen solved = 324, spread = 324, legal = 324; time = 0.00s Info: at iteration #3, type GSR: wirelen solved = 324, spread = 324, legal = 324; time = 0.00s Info: at iteration #3, type ALL: wirelen solved = 171, spread = 289, legal = 353; time = 0.00s Info: at iteration #4, type rPLL: wirelen solved = 300, spread = 300, legal = 353; time = 0.00s Info: at iteration #4, type SLICE: wirelen solved = 234, spread = 301, legal = 313; time = 0.00s Info: at iteration #4, type VCC: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #4, type GND: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #4, type GSR: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s Info: at iteration #4, type ALL: wirelen solved = 177, spread = 248, legal = 299; time = 0.00s Info: at iteration #5, type rPLL: wirelen solved = 253, spread = 253, legal = 307; time = 0.00s Info: at iteration #5, type SLICE: wirelen solved = 227, spread = 303, legal = 307; time = 0.00s Info: at iteration #5, type VCC: wirelen solved = 307, spread = 307, legal = 307; time = 0.00s Info: at iteration #5, type GND: wirelen solved = 307, spread = 307, legal = 307; time = 0.00s Info: at iteration #5, type GSR: wirelen solved = 307, spread = 307, legal = 307; time = 0.00s Info: at iteration #5, type ALL: wirelen solved = 173, spread = 249, legal = 312; time = 0.00s Info: at iteration #6, type rPLL: wirelen solved = 258, spread = 258, legal = 312; time = 0.00s Info: at iteration #6, type SLICE: wirelen solved = 234, spread = 314, legal = 314; time = 0.00s Info: at iteration #6, type VCC: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #6, type GND: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #6, type GSR: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #6, type ALL: wirelen solved = 180, spread = 261, legal = 321; time = 0.00s Info: at iteration #7, type rPLL: wirelen solved = 267, spread = 267, legal = 321; time = 0.00s Info: at iteration #7, type SLICE: wirelen solved = 229, spread = 303, legal = 310; time = 0.00s Info: at iteration #7, type VCC: wirelen solved = 310, spread = 310, legal = 310; time = 0.00s Info: at iteration #7, type GND: wirelen solved = 310, spread = 310, legal = 310; time = 0.00s Info: at iteration #7, type GSR: wirelen solved = 310, spread = 310, legal = 310; time = 0.00s Info: at iteration #7, type ALL: wirelen solved = 173, spread = 250, legal = 308; time = 0.00s Info: at iteration #8, type rPLL: wirelen solved = 254, spread = 254, legal = 308; time = 0.00s Info: at iteration #8, type SLICE: wirelen solved = 258, spread = 304, legal = 311; time = 0.00s Info: at iteration #8, type VCC: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #8, type GND: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #8, type GSR: wirelen solved = 311, spread = 311, legal = 311; time = 0.00s Info: at iteration #8, type ALL: wirelen solved = 205, spread = 251, legal = 315; time = 0.00s Info: at iteration #9, type rPLL: wirelen solved = 261, spread = 261, legal = 309; time = 0.00s Info: at iteration #9, type SLICE: wirelen solved = 225, spread = 310, legal = 314; time = 0.00s Info: at iteration #9, type VCC: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #9, type GND: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #9, type GSR: wirelen solved = 314, spread = 314, legal = 314; time = 0.00s Info: at iteration #9, type ALL: wirelen solved = 178, spread = 254, legal = 311; time = 0.00s Info: HeAP Placer Time: 0.35s Info: of which solving equations: 0.04s Info: of which spreading cells: 0.01s Info: of which strict legalisation: 0.01s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 33, wirelen = 299 Info: at iteration #5: temp = 0.000000, timing cost = 47, wirelen = 268 Info: at iteration #5: temp = 0.000000, timing cost = 47, wirelen = 268 Info: SA placement time 0.03s Info: Max frequency for clock 'pll_out_clk': 316.86 MHz (PASS at 12.00 MHz) Info: Max delay -> : 30.02 ns Info: Max delay posedge pll_out_clk -> : 7.89 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 53311, 54773) |*+ Info: [ 54773, 56235) |+ Info: [ 56235, 57697) |***+ Info: [ 57697, 59159) | Info: [ 59159, 60621) |******+ Info: [ 60621, 62083) | Info: [ 62083, 63545) | Info: [ 63545, 65007) | Info: [ 65007, 66469) | Info: [ 66469, 67931) | Info: [ 67931, 69393) | Info: [ 69393, 70855) | Info: [ 70855, 72317) | Info: [ 72317, 73779) | Info: [ 73779, 75241) | Info: [ 75241, 76703) |*+ Info: [ 76703, 78165) |+ Info: [ 78165, 79627) |**+ Info: [ 79627, 81089) |************************+ Info: [ 81089, 82551) |************************************************************ Info: Checksum: 0xf097279d Info: Find global nets... Info: Routing globals... Info: Route net ADC_D_IBUF_I_O[4], use clock #-1. Info: Net ADC_D_IBUF_I_O[4] is routed. Info: Route net rpll.clkoutd_o, use clock #-1. Info: Net rpll.clkoutd_o is routed. Info: Route net rpll.clkoutd3_o, use clock #-1. Info: Net rpll.clkoutd3_o is routed. Info: Route net rpll.clkoutp_o, use clock #-1. Info: Net rpll.clkoutp_o is routed. Info: Route net pll_out_clk, use clock #0. Info: Net pll_out_clk is routed. Info: Routing.. Info: Setting up routing queue. Info: Routing 279 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 512 | 233 279 | 233 279 | 0| 2.87 2.87| Info: Routing complete. Info: Router1 time 2.87s Info: Checksum: 0x58d6f15c Info: Critical path report for clock 'pll_out_clk' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source cnt_DFF_Q_4_DFFLC.Q Info: 0.8 1.3 Net KEY0_IBUF_I_O[1] budget 82.875336 ns (41,24) -> (40,24) Info: Sink rpll.gw_gnd_ALU_I0_12_ALULC.B Info: Defined in: Info: top.v:28.11-28.14 Info: 1.1 2.4 Source rpll.gw_gnd_ALU_I0_12_ALULC.F Info: 0.8 3.2 Net cnt_DFF_Q_D[24] budget 40.888668 ns (40,24) -> (41,24) Info: Sink cnt_DFF_Q_4_DFFLC.A Info: Defined in: Info: top.v:32.10-32.17 Info: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/arith_map.v:34.28-34.29 Info: 0.0 3.2 Setup cnt_DFF_Q_4_DFFLC.A Info: 1.6 ns logic, 1.6 ns routing Info: Critical path report for cross-domain path '' -> '': Info: curr total Info: 0.0 0.0 Source KEY0_IBUF_I$iob.O Info: 14.1 14.1 Net KEY0_IBUF_I_O[2] budget 83.333336 ns (7,0) -> (41,25) Info: Sink LED_OBUF_O_I_LUT3_F_LC.C Info: Defined in: Info: D:\Gowin\oss-cad-suite\bin\../share/yosys/gowin/cells_map.v:130.20-130.21 Info: 0.8 14.9 Source LED_OBUF_O_I_LUT3_F_LC.F Info: 3.4 18.2 Net LED_OBUF_O_I budget 40.888668 ns (41,25) -> (32,28) Info: Sink LED_OBUF_O$iob.I Info: 0.8 ns logic, 17.4 ns routing Info: Critical path report for cross-domain path 'posedge pll_out_clk' -> '': Info: curr total Info: 0.5 0.5 Source cnt_DFF_Q_DFFLC.Q Info: 0.5 0.9 Net cnt[28] budget 82.875336 ns (41,24) -> (41,25) Info: Sink LED_OBUF_O_I_LUT3_F_LC.B Info: Defined in: Info: top.v:28.11-28.14 Info: 1.1 2.0 Source LED_OBUF_O_I_LUT3_F_LC.F Info: 3.4 5.4 Net LED_OBUF_O_I budget 40.888668 ns (41,25) -> (32,28) Info: Sink LED_OBUF_O$iob.I Info: 1.6 ns logic, 3.8 ns routing Info: Max frequency for clock 'pll_out_clk': 315.86 MHz (PASS at 12.00 MHz) Info: Max delay -> : 18.23 ns Info: Max delay posedge pll_out_clk -> : 5.39 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 65103, 65994) |*+ Info: [ 65994, 66885) |+ Info: [ 66885, 67776) |****+ Info: [ 67776, 68667) | Info: [ 68667, 69558) |*******+ Info: [ 69558, 70449) | Info: [ 70449, 71340) | Info: [ 71340, 72231) | Info: [ 72231, 73122) | Info: [ 73122, 74013) | Info: [ 74013, 74904) | Info: [ 74904, 75795) | Info: [ 75795, 76686) | Info: [ 76686, 77577) | Info: [ 77577, 78468) |*+ Info: [ 78468, 79359) | Info: [ 79359, 80250) |****+ Info: [ 80250, 81141) |*****************************+ Info: [ 81141, 82032) |****************+ Info: [ 82032, 82923) |************************************************************ Info: Program finished normally. [OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>
Программа nextpnr-gowin размещает логику из созданного ранее результата синтеза output\out-synth.json и создает новый файл output\out-pnr.json. Всё это делается под конкретную микросхему FPGA GW1NR-UV9QN88C6/I5 (на плате Марсоход3GW стоит именно она) и с учетом физической привязки сигналов к конкретным пинам чипа из файла board.cst
10. Упаковываем битстрим для дальнейшей загрузки в ПЛИС:
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>gowin_pack -d GW1NR-UV9QN88C6/I5 -o output\out-pack.fs output\out-pnr.json
[OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>gowin_pack -d GW1NR-UV9QN88C6/I5 -o output\out-pack.fs output\out-pnr.json :219: Warning: Numpy built with MINGW-W64 on Windows 64 bits is experimental, and only available for testing. You are advised not to use it for production. CRASHES ARE TO BE EXPECTED - PLEASE REPORT THEM TO NUMPY DEVELOPERS [OSS CAD Suite] D:\Gowin\M3GW\_clk_pll_counter\src>
Получим файл для программатора output\out-pack.fs. Остается только загрузить этот файл в FPGA. В пакет программ OSS CAD Suite входит так же и программатор.
11. Загружаем файл битстрима в FPGA Gowin платы Марсоход3GW
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>openFPGALoader output/out-pack.fs
Можно так же записать этот битстрим не в статическую память ПЛИС, а во встроенную флэш память микросхемы, так чтобы она стартовала сразу после включения. Используйте дополнительный параметр "-f":
[OSS CAD Suite] D:\Gowin\Marsohod3GW\_clk_pll_counter\src>openFPGALoader -f output/out-pack.fs
К сожалению, на последнем шаге программирования вы можете столкнуться с некоторыми трудностями, а именно, программа openFPGALoader не обнаруживает встроенный на нашей плате программатор FTDI FT2232H.
Это проблема c драйвером.
Чтобы это сработало, нужно заменить драйвер последовательного порта на драйвер libusbK.sys. Сделать это проще всего с помощью сторонней программы Zadig (https://zadig.akeo.ie/)
После замены драйвера загрузка ПЛИС программатором из комплекта OSS CAD Suite идет без проблем.
Вот пожалуй и всё! Использование OSS CAD Suite для создания проектов для FPGA Gowin несложно и вполне возможно.
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