ТЕМА: Первый проект, почему не работает?

module vga_sync_generator (
input wire clk,
output wire hsync,
output wire vsync,
output wire blank_n
);


reg [10:0] countH;
reg [10:0] countV;


parameter H_ACTIVE_VIDEO = 640;
parameter H_FRONT_PORCH = 24;
parameter H_SYNC_PULSE = 95;
parameter H_BACK_PORCH = 48;

parameter H_BLANK = H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;
parameter H_TOTAL = H_ACTIVE_VIDEO + H_BLANK;

parameter V_ACTIVE_VIDEO = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC_PULSE = 2;
parameter V_BACK_PORCH = 33;

parameter V_BLANK = V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;
parameter V_TOTAL = V_ACTIVE_VIDEO + V_BLANK;

//сигнал активности изображения
assign blank_n = ~((countH < H_BLANK) || (countV < V_BLANK));

//импульс горизонтальной синхронизации
assign hsync = ~((countH >= H_FRONT_PORCH-1) && (countH <= H_FRONT_PORCH + H_SYNC_PULSE-1));

//импульс вертикальной синхронизации
assign vsync = (countV >= V_FRONT_PORCH-1) && (countV <= V_FRONT_PORCH + V_SYNC_PULSE-1);

// countH и countV
always @(posedge clk)
begin
if (countH < H_TOTAL)
countH <= countH + 1'b1;
else
countH <= 0;
end

always @(posedge hsync)
begin
if (countV < V_TOTAL)
countV <= countV + 1'b1;
else
countV <= 0;
end
endmodule

module color (
input blank_n,
output [2:0]rgb
);

reg [1:0] count_color;

assign rgb = count_color;


always @(blank_n)
begin
if (blank_n)
count_color = 3'b111;
else
count_color = 3'b0;
end
endmodule