ТЕМА: EPM240T100C5 не работает RAM память

module dds_generator(clk,signal_output);
input wire clk;
output wire [7:0] signal_output;
reg [31:0] phase_acumulator;
initial phase_acumulator = 32'd0;
//assign signal_output = ~phase_acumulator[31:24];
 ram_1port sin(
   .address(phase_acumulator[31:24]),
   .data(),
   .outclock(clk),
   .we(1'b0),
   .q(signal_output));
always@(posedge clk ) begin
 phase_acumulator <= phase_acumulator + 32'd85899346;
end
 endmodule

// генератор трехфазного синусоидального сигнала со смещением фаз относительно друг друга

module phase_gen (

input wire clk,
input wire sine_clk,
input wire amp_en,
input wire [2:0]amp,
output reg [2:0]phase
);

reg [7:0]pwm_count;		 //счетчик ШИМ
reg [6:0]sine_code;		 //перебирает значения таблицы синуса
reg [4:0]count_mod;		 //содержит порядковый номер точки
reg [7:0]quarter_sine;	 //содержит текущее значение четверти из таблицы синуса
reg [7:0]sine; 			 //содержит текущее значение синуса
reg [6:0]sine_count;	 //счетчик точек синуса
reg [1:0]phase_count;	 //счетчик фаз
reg [2:0]amplitude;
reg [7:0]sine_out;


always @*
begin
	case(count_mod)		 // таблица четверти волны 
5'd0:	quarter_sine=8'd131;
5'd1:	quarter_sine=8'd134;	
5'd2:	quarter_sine=8'd146;
5'd3:	quarter_sine=8'd152;
5'd4:	quarter_sine=8'd158;
5'd5:	quarter_sine=8'd165;
5'd6:	quarter_sine=8'd170;
5'd7:	quarter_sine=8'd176;
5'd8:	quarter_sine=8'd180;
5'd9:	quarter_sine=8'd188;
5'd10:	quarter_sine=8'd193;
5'd11:	quarter_sine=8'd198;
5'd12:	quarter_sine=8'd203;
5'd13:	quarter_sine=8'd208;
5'd14:	quarter_sine=8'd213;
5'd15:	quarter_sine=8'd218;
5'd16:	quarter_sine=8'd222;
5'd17:	quarter_sine=8'd226;
5'd18:	quarter_sine=8'd230;
5'd19:	quarter_sine=8'd234;
5'd20:	quarter_sine=8'd237;
5'd21:	quarter_sine=8'd240;
5'd22:	quarter_sine=8'd243;
5'd23:	quarter_sine=8'd245;
5'd24:	quarter_sine=8'd248;
5'd25:	quarter_sine=8'd250;
5'd26:	quarter_sine=8'd251;
5'd27:	quarter_sine=8'd253;
5'd28:	quarter_sine=8'd254;
5'd29:	quarter_sine=8'd254;
5'd30:	quarter_sine=8'd255;
5'd31:	quarter_sine=8'd255;
	endcase
	case(sine_code[6]) // формирует нижнюю полуволну синуса
0:	sine=quarter_sine;
1:	sine=(8'd255 - quarter_sine);
	endcase
	case(sine_code[5])// инвертирует значение счетчика синуса при нечетной четверти
0:	count_mod=sine_code[4:0];
1:	count_mod=~sine_code[4:0];
	endcase
	case(phase_count) // разводит фазы на нужный градус
0:	sine_code=sine_count;
1:	sine_code=sine_count + 7'd43;	//~120
2:	sine_code=sine_count + 7'd85;	//~240
3:	sine_code=sine_count;
	endcase

end
always @(posedge clk)
begin
	if(amp_en)
	begin
	amplitude<=amp;
	end
	case(amplitude)
0:	sine_out<=sine>>3;
1:	sine_out<=sine>>2;
2:	sine_out<=(sine>>2)+(sine>>3);
3:	sine_out<=sine>>1;
4:	sine_out<=(sine>>1)+(sine>>3);
5: 	sine_out<=(sine>>1)+(sine>>2);
6:	sine_out<=(sine>>1)+(sine>>2)+(sine>>3);
7:	sine_out<=sine;
	endcase
	pwm_count <= pwm_count + 1; // инкрементируем счетчик ШИМ 
	if(phase_count < 2)	// ограничиваем счетчик фаз тремя положениями 0,1,2
	phase_count <= phase_count + 1;
	else
	phase_count <= 0; 
	if(phase_count == 2'd0)// расчет ШИМ для фазы №1
	begin
		if(pwm_count <= sine_out)
		phase[0] <= 1;
		else
		phase[0] <= 0;
	end
	if(phase_count == 2'd1)// расчет ШИМ для фазы №2
	begin
		if(pwm_count <= sine_out)
		phase[1] <= 1;
		else
		phase[1] <= 0;
	end
	if(phase_count == 2'd2)// расчет ШИМ для фазы №3
	begin
		if(pwm_count <= sine_out)
		phase[2] <= 1;
		else
		phase[2] <= 0;
	end
end
always @(posedge sine_clk)
begin
sine_count <= sine_count + 1; // инкрементируем счетчик точек синуса по внешнему тактовому сигналу.
end
	
endmodule	

module dac(DACout, clk, DACin);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input clk;
input [6:0]DACin;


reg [8:0] DeltaAdder; // Output of Delta adder
reg [8:0] SigmaAdder; // Output of Sigma adder
reg [8:0] SigmaLatch; // Latches output of Sigma adder
reg [8:0] DeltaB; // B input of Delta adder

always @(SigmaLatch) DeltaB = {SigmaLatch[8], SigmaLatch[8]} << (7);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clk)
begin
SigmaLatch <= SigmaAdder;
DACout <=  SigmaLatch[8];
end
endmodule

module dds_gen (clk,signal_output,signal_input,gnd);
input wire clk; // 50Mhz
input wire [7:0] signal_input;
output wire [7:0] signal_output;
output wire [7:0]  gnd;
reg [31:0] phase_acumulator;
initial phase_acumulator = 32'd0;
//----------------------------------------------------------------------------------------------------------
always@(posedge clk ) begin
 phase_acumulator <= phase_acumulator + 32'd8590; // 100khz 
end
//---------------------------------------------------------------------------------------------------------
bufif0 bufif0_0 (gnd[0],signal_input[0],phase_acumulator[24]);
bufif0 bufif0_1 (gnd[1],signal_input[1],phase_acumulator[25]);
bufif0 bufif0_2 (gnd[2],signal_input[2],phase_acumulator[26]);
bufif0 bufif0_3 (gnd[3],signal_input[3],phase_acumulator[27]);
bufif0 bufif0_4 (gnd[4],signal_input[4],phase_acumulator[28]);
bufif0 bufif0_5 (gnd[5],signal_input[5],phase_acumulator[29]);
bufif0 bufif0_6 (gnd[6],signal_input[6],phase_acumulator[30]);
bufif0 bufif0_7 (gnd[7],signal_input[7],phase_acumulator[31]);
//----------------------------------------------------------------------------------------------------------
bufif1 bufif1_0 (signal_output[0],signal_input[0],phase_acumulator[24]);
bufif1 bufif1_1 (signal_output[1],signal_input[1],phase_acumulator[25]);
bufif1 bufif1_2 (signal_output[2],signal_input[2],phase_acumulator[26]);
bufif1 bufif1_3 (signal_output[3],signal_input[3],phase_acumulator[27]);
bufif1 bufif1_4 (signal_output[4],signal_input[4],phase_acumulator[28]);
bufif1 bufif1_5 (signal_output[5],signal_input[5],phase_acumulator[29]);
bufif1 bufif1_6 (signal_output[6],signal_input[6],phase_acumulator[30]);
bufif1 bufif1_7 (signal_output[7],signal_input[7],phase_acumulator[31]);
 endmodule