ТЕМА: Как писать тесты?

library ieee;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity ddcsim_tb is
end ddcsim_tb;

architecture TB_ARCHITECTURE of ddcsim_tb is
	-- Component declaration of the tested unit
	component ddcsim
	port(
		CLK_100MHZ : in STD_LOGIC;
		RX : in STD_LOGIC;
		ADCCLK : out STD_LOGIC;
		AUDI : out STD_LOGIC;
		AUDQ : out STD_LOGIC;
		TX : out STD_LOGIC;
		HL : out STD_LOGIC_VECTOR(3 downto 0) );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal CLK_100MHZ : STD_LOGIC;
	signal RX : STD_LOGIC;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal ADCCLK : STD_LOGIC;
	signal AUDI : STD_LOGIC;
	signal AUDQ : STD_LOGIC;
	signal TX : STD_LOGIC;
	signal HL : STD_LOGIC_VECTOR(3 downto 0);

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : ddcsim
		port map (
			CLK_100MHZ => CLK_100MHZ,
			RX => RX,
			ADCCLK => ADCCLK,
			AUDI => AUDI,
			AUDQ => AUDQ,
			TX => TX,
			HL => HL
		);

	-- Add your stimulus here ...

stimulus: process
begin
	RX <= '1';
    wait for 500 ns;
---	RX <= '0';
    wait for 200 ns;
	RX <= '1';
    wait for 200 ns;

---	wait;
end process;

clk_gen: process
begin
		CLK_100MHZ <= '0';
		wait for 5 ns;
		CLK_100MHZ <= '1';
		wait for 5 ns;
end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_ddcsim of ddcsim_tb is
	for TB_ARCHITECTURE
		for UUT : ddcsim
			use entity work.ddcsim(ddcsim);
		end for;
	end for;
end TESTBENCH_FOR_ddcsim;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity my_ff_code is
     port(
         R : in STD_LOGIC;
         S : in STD_LOGIC;
         Q : out STD_LOGIC
         );
end my_ff_code;

architecture my_ff_code_arch of my_ff_code is
begin
    Q <= '1' when S='1' else
         '0' when R='1' and S='0';
end my_ff_code_arch;

library ieee;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity my_ff_code_tb is
end my_ff_code_tb;

architecture TB_ARCHITECTURE of my_ff_code_tb is
	-- Component declaration of the tested unit
	component my_ff_code
	port(
		R : in STD_LOGIC;
		S : in STD_LOGIC;
		Q : out STD_LOGIC );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal R : STD_LOGIC;
	signal S : STD_LOGIC;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal Q : STD_LOGIC;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : my_ff_code
		port map (
			R => R,
			S => S,
			Q => Q
		);

	-- Add your stimulus here ...
stimulus: process
begin
	S <= '1';
	R <= '0';
    wait for 1 ms;
	S <= '0';
	R <= '1';
    wait for 1 ms;
	S <= '1';
	R <= '0';
    wait for 1 ms;
	S <= '0';
	R <= '1';
    wait for 1 ms;
	S <= '0';
	R <= '0';
    wait;

end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_my_ff_code of my_ff_code_tb is
	for TB_ARCHITECTURE
		for UUT : my_ff_code
			use entity work.my_ff_code(my_ff_code_arch);
		end for;
	end for;
end TESTBENCH_FOR_my_ff_code;