ТЕМА: SPI

module spi_send
(
input  clk_in,
output wire sclk_out,
output reg mosi,
input miso,
output reg  ss
);
reg [11:0] count = 11'b00000000000;
reg [7:0]  data = 8'b11110000;
reg [4:0]  i = 4'b0;


//Baud 19200 = speed 833
assign sclk_out = clk_in;

always @(posedge clk_in)
begin

count <= count + 1'b1;	

if(count == 833)
	begin
ss = 1'b0;//начало передачи бита
if (ss == 0)
begin
data[7:0] <= {data[6:0],mosi};	
	count <= 0;
	i <= i + 1;
	ss = 1'b0;
if (i > 7)	
 begin
i <= 0;
ss = 1'b1;//конец передачи бита
 end	
end 
   end
end
endmodule