ТЕМА: 3-х фазный генератор

module Phase_Counter(clock, reset, phase,en_out, en_in);

//********************************
//******** I/O definitions *******
//********************************
input wire 		clock;
input wire 		reset;
input wire 		en_in;
output wire 		phase;
output wire 		en_out;
//********************************

//********************************
//***** Internal definitions *****
//********************************
reg[7:0] counter;
reg  en_flag;
//********************************

initial
begin
en_flag<=0;
end

always @(posedge clock or negedge reset)
begin
			if(!reset)  // Reset counter
			begin
				counter<=8'd0;	
			end
		
			
			else
			begin
				if(en_in)
					begin
						counter<=counter + 1;
						if(counter==45)
							en_flag<=1;
					end
				
			end
	
end
	



assign en_out = 	en_flag;
assign phase  = (counter<=80);

endmodule
				

module ph_gen(clk,rst,f);
input clk,rst;
output [2:0] f;
reg [2:0]cnt;

always @(posedge clk or negedge rst )
  if(!rst)
    cnt <= 0;
  else
	if(cnt==5)
       cnt <= 0;
    else  
	   cnt<=cnt+1;

assign f[0] = (cnt[0] || cnt[1]) & !cnt[2];
assign f[1] = cnt[1] || (!cnt[0] & cnt[2]);
assign f[2] = cnt[2]|| (cnt[0] & cnt[1]);
endmodule