ТЕМА: VHDL2Verilog

process(clk, Q)
	begin
		if (clk'event and clk = '1') then
			if (ena = '1') then
				delay_pipe(0) <= Q;
				for n in 1 to PipeLength -1 loop
					delay_pipe(n) <= delay_pipe(n -1);
				end loop;
			end if;
		end if;
	end process;
	dQ <= delay_pipe(PipeLength -1);

always	@(posedge clk) begin
	if (ena) begin
		delay_pipe[0] <= Q;	
		for (n = 1; n < PipeLength; n = n + 1)
      			delay_pipe[n] <= delay_pipe[n - 1];
  	end
end
assign	dQ = delay_pipe[PipeLength - 1];