ТЕМА: 2 энкодера. Скорость/положение

module WriteToDAC(Clk, CS, WR);

input Clk;
output reg WR = 1'b1;
output reg CS = 1'b1;

reg [1:0] state = 2'b0;

always @(posedge Clk ) 

	if(state == 2'b00)
		begin
			CS <= 1'b0; 
			WR <= 1'b0;
			state <=  state + 1'b1;
		end
	else 
	
	if(state == 2'b01) 
		begin
			state <=  state + 1'b1;				
		end
	else 
	
	if(state == 2'b10)
		begin
			CS <= ~CS; 
			WR <= ~WR;
			state <=  state + 1'b1;
		end
	else 
	
	if(state == 2'b11)
		begin
			state <= 2'b0;
		end	
	else state <= 2'b0;
	
endmodule 

module x4enc2(
	input clk,    
	input A,
	input B,
	output reg step,
	output reg dir
);

reg [1:0] Ar, Br;  

wire A_posedge = (Ar==2'b01);  // now we can detect A rising edges
wire A_negedge = (Ar==2'b10);  // and falling edges
wire B_posedge = (Br==2'b01);  // now we can detect B rising edges
wire B_negedge = (Br==2'b10);  // and falling edges

always @ (posedge clk)
begin
	Ar <= {Ar[0], A};
	Br <= {Br[0], B};
	if (A_posedge)
	begin
		step <= 1;
		if (~Br[1]) 
			dir<=1; // A leads B
		else 
			dir<=0;
		end
	else 
	if (A_negedge)
	begin
		step <= 1;
		if (Br[1]) 
			dir<=1;
		else 
			dir<=0;
	end
	else 
	if (B_posedge)
	begin
		step <= 1;
		if (Ar[1]) 
			dir<=1;
		else 
			dir<=0;
	end
	else 
	if (B_negedge)
	begin
		step <= 1;
		if (~Ar[1]) 
			dir<=1;
		else 
			dir<=0;
		end
	else 
	step <= 0;
end
endmodule

module quadEncoder  
#(
		parameter C_DWIDTH 		= 32,
		parameter C_SPDWIDTH	=	16	
 ) 
 (
 		input																		clk, 
 		input																		clear_n, 
 		input																		sample_clk, 
 		input																		quadA, 
 		input																		quadB, 
 		output	reg signed	[C_DWIDTH - 1:0]		count, 
 		output			signed 	[C_SPDWIDTH - 1:0]	speed
 		
 	);

	reg 	[2:0] 						quadA_delayed, quadB_delayed;	
	reg 	[C_DWIDTH - 1:0] 	last_count;
	wire										count_enable;
	wire										count_direction;
	
	always @(posedge clk) begin : direction_detect
		quadA_delayed <= {quadA_delayed[1:0], quadA};
		quadB_delayed <= {quadB_delayed[1:0], quadB};
	end	

	always @(posedge clk or negedge clear_n)
		if (!clear_n)
			count <= 'd0;
		else if (count_enable)
			count <= (count_direction) ? count + 1'b1 : count - 1'b1;  

	always @(posedge sample_clk)
		last_count <= count;

	assign speed 						= count - last_count;
	assign count_enable			= quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
	assign count_direction	= quadA_delayed[1] ^ quadB_delayed[2];

	
endmodule