Здравствуйте! Ошибка в коде, ругается на то, что объект "dff" используется, но не зарегестрирован. Помогите пожалуйста это исправить. Где и что нужно написать?
Вот сам код:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library LPM;
use LPM.lpm_components.ALL;
entity vgacon is
generic
(
ramfile : string := "UNUSED"
);
port( clock : in std_logic;
resetn : in std_logic;
row, col : in std_logic_vector( 5 downto 0 );
colour : in std_logic_vector( 2 downto 0 );
do_write : in std_logic;
done_write : out std_logic;
hsync, vsync : out std_logic;
data_r : out std_logic;
data_g : out std_logic;
data_b : out std_logic;
done_screen : out std_logic
);
end vgacon;
architecture ComponentLevel of vgacon is
signal Reset : std_logic;
signal EnableVert_din, EnableVert : std_logic;
signal ResetVert_din, ResetVert : std_logic;
signal CounterHoriz, CounterVert : std_logic_vector( 9 downto 0 );
signal CounterTen : std_logic_vector( 3 downto 0 );
signal EnableCol_din, EnableCol : std_logic;
signal CounterCol, CounterRow : std_logic_vector( 5 downto 0 );
signal RAMreadAddress , RAMwriteAddress_din,
RAMwriteAddress, RAMaddress_din,
RAMaddress : std_logic_vector(11 downto 0 );
signal WriteStart : std_logic;
signal WriteControl : std_logic_vector( 1 downto 0 );
signal Reading_din, Reading : std_logic;
signal HorizValid_pipe1, VertValid_pipe1,
ViewValid_pipe2, ViewValid_pipe3 : std_logic;
signal PixelDataIn, PixelDataOut_pipe3 : std_logic_vector( 0 downto 0 );
signal DataR_din, hsync_din, vsync_din : std_logic;
signal High : std_logic;
signal Low2 : std_logic_vector( 1 downto 0 );
signal Low4 : std_logic_vector( 3 downto 0 );
constant C_VERT_NUM_PIXELS : integer := 480;
constant C_VERT_SYNC_START : integer := 493;
constant C_VERT_SYNC_END : integer := 494;
constant C_VERT_TOTAL_COUNT : integer := 525;
constant C_HORZ_NUM_PIXELS : integer := 640;
constant C_HORZ_SYNC_START : integer := 659;
constant C_HORZ_SYNC_END : integer := 755;
constant C_HORZ_TOTAL_COUNT : integer := 800;
begin
High <= '1';
Low4 <= "0000";
Low2 <= "00";
Reset <= NOT Resetn;
EnableVert_din <= '1' when CounterHoriz = (C_HORZ_TOTAL_COUNT-2) else '0';
dff1: dff PORT MAP ( d => EnableVert_din, q => EnableVert, clk => Clock, (((Вот в этом месте выдаёт ошибку)))
clrn => Resetn, prn => High );
ResetVert_din <= '1' when ( EnableVert_din = '1' and
CounterVert= (C_VERT_TOTAL_COUNT-1) ) else '0';
dff2: dff PORT MAP ( d => ResetVert_din , q => ResetVert , clk => Clock,
clrn => Resetn, prn => High );
Horizontal: lpm_counter
GENERIC MAP ( lpm_width => 10 )
PORT MAP ( clock => Clock,
aclr => Reset,
sclr => EnableVert, -- Reset Horiz on next line
q => CounterHoriz );
Vertical: lpm_counter
GENERIC MAP ( lpm_width => 10 )
PORT MAP ( clock => Clock,
aclr => Reset,
sclr => ResetVert,
q => CounterVert,
cnt_en => EnableVert );
Count10: lpm_counter
GENERIC MAP ( lpm_width => 4 )
PORT MAP ( clock => Clock,
aclr => Reset,
sclr => EnableCol,
q => CounterTen );
EnableCol_din <= '1' when CounterTen="1000" else '0';
dff3: dff PORT MAP ( d => EnableCol_din, q => EnableCol, clk => Clock,
clrn => Resetn, prn => High );
CountCol: lpm_counter
GENERIC MAP ( lpm_width => 6 )
PORT MAP ( clock => Clock,
aclr => Reset,
sclr => EnableVert,
q => CounterCol,
cnt_en => EnableCol );
CounterRow <= CounterVert(8 downto 3);
process (Clock, Reset)
begin
if Reset = '1' then
HorizValid_pipe1 <= '0';
VertValid_pipe1 <= '0';
ViewValid_pipe2 <= '0';
ViewValid_pipe3 <= '0';
elsif Clock'Event and Clock='1' then
if CounterHoriz >= 0 and CounterHoriz < C_HORZ_NUM_PIXELS then
HorizValid_pipe1 <= '1';
else
HorizValid_pipe1 <= '0';
end if;
if CounterVert >= 0 and CounterVert < C_VERT_NUM_PIXELS then
VertValid_pipe1 <= '1';
else
VertValid_pipe1 <= '0';
end if;
ViewValid_pipe2 <= HorizValid_pipe1 and VertValid_pipe1;
ViewValid_pipe3 <= ViewValid_pipe2;
end if;
end process;
Reading_din <= '1' when ( CounterHoriz <= (C_HORZ_NUM_PIXELS +20) or
CounterHoriz >= (C_HORZ_TOTAL_COUNT-20) ) else '0';
dff5: dff PORT MAP ( d => Reading_din, q => Reading, clk => Clock,
prn => Resetn, clrn => High );
RAMreadAddress( 11 downto 6 ) <= CounterRow;
RAMreadAddress( 5 downto 0 ) <= CounterCol;
RAMwriteAddress_din(11 downto 6 ) <= row;
RAMwriteAddress_din( 5 downto 0 ) <= col;
reg1: lpm_ff
GENERIC MAP ( lpm_width => 12 )
PORT MAP ( data => RAMwriteAddress_din,
q => RAMwriteAddress,
clock => Clock,
aclr => Reset );
WriteStart <= '1' when ( do_write='1' and Reading='0' ) else '0';
done_write <= NOT Reading;
srg1: lpm_shiftreg
GENERIC MAP ( lpm_width => 2 )
PORT MAP ( clock => Clock,
data => Low2,
aclr => Reset,
shiftin => WriteStart,
q => WriteControl );
srg2: lpm_shiftreg
GENERIC MAP ( lpm_width => 2 )
PORT MAP ( clock => Clock,
data => Low2,
aclr => Reset,
shiftin => colour(0),
shiftout => PixelDataIn(0) );
RAMaddress_din <= RAMreadAddress WHEN WriteControl(0)='0' ELSE RAMwriteAddress;
reg2: lpm_ff
GENERIC MAP ( lpm_width => 12 )
PORT MAP ( data => RAMaddress_din,
q => RAMaddress,
clock => Clock,
aclr => Reset );
VideoRam: lpm_ram_dq
GENERIC MAP ( lpm_widthad => 12, -- 64x64 SuperPixel grid
lpm_outdata => "REGISTERED", -- register the output
lpm_indata => "REGISTERED", -- and input as well
lpm_address_control => "REGISTERED", -- as add/cont lines.
lpm_file => ramfile,
lpm_width => 1 )
PORT MAP ( data => PixelDataIn , address => RAMaddress,
we => WriteControl(1), q => PixelDataOut_pipe3,
inclock => Clock , outclock => Clock );
DataR_din <= ViewValid_pipe3 AND PixelDataOut_pipe3( 0 );
dff8: dff port map ( d => DataR_din, q => data_g, clk => Clock,
clrn => Resetn, prn => High ); -- data_g -> 4 cycles of latency
data_r <= '0';
data_b <= '0';
hsync_din <= '0' when ( CounterHoriz >= C_HORZ_SYNC_START and
CounterHoriz <= C_HORZ_SYNC_END ) else '1';
srg3: lpm_shiftreg
GENERIC MAP ( lpm_width => 4 )
PORT MAP ( clock => Clock,
data => Low4,
aset => Reset,
shiftin => hsync_din,
shiftout => hsync );
vsync_din <= '0' when ( CounterVert >= C_VERT_SYNC_START and
CounterVert <= C_VERT_SYNC_END ) else '1';
sr4: lpm_shiftreg
GENERIC MAP ( lpm_width => 4 )
PORT MAP ( clock => Clock,
data => Low4,
aset => Reset,
shiftin => vsync_din,
shiftout => vsync );
done_screen <= ResetVert;
end ComponentLevel;
