ТЕМА: Проблема с 'case statement'

module uart(
	input wire RX,
	input wire TX,
	input wire CLK100MHZ,	
	output wire LED0,
	output wire LED1,
	output wire LED2,
	output wire [7:0] data,
	output wire data_ready
);
	wire clk;
	reg   [3:0] led = 4'b0;
	reg	[7:0] rx_queue[0:7];
	reg	[3:0]	 rx_queue_rp = 0;
	
	divider freq_div(.clk_in (CLK100MHZ), .clk_out (clk));
	uart_rx rx_(.rx (RX), .clk (clk), .data (data), .data_ready (data_ready));
	
	always @(posedge data_ready)
		begin
			rx_queue[rx_queue_rp] <= data;
			rx_queue_rp <= rx_queue_rp + 1'b1;
			case(data)
				"\r": 
					begin
						led[0] = 1;
					end
				"2":
					begin
						led[1] = 1;
					end
				"1":
					begin
						led[2] = 1;
					end
				"0":	
					begin
						led[0] = 0;
						led[1] = 0;
						led[2] = 0;
					end				
			endcase			
		end
			
	assign LED0 = led[0];
	assign LED1 = led[1];
	assign LED2 = led[2];
	
endmodule

		case(data)
				"\r": 
					begin
						led[0] = 1;
					end
				"2":
					begin
						led[1] = 1;
					end
				//"1":
					//begin
						//led[2] = 1;
					//end
				"0":	
					begin
						led[0] = 0;
						led[1] = 0;
						led[2] = 0;
					end				
			endcase			
		end