ТЕМА: Вопрос по симуляции (ModelSlim)

`timescale 1ns / 100ps // Clock - 1ns, Precession 100ps (Не принципиально. Это тест)

module test;

	reg clk;

	root root_test(clk);
	
	always
	#10 clk = ~clk;
	
	initial
	begin
		clk=0;
	end

endmodule

// ***********************
//
// Главный модуль
//
// ***********************

module root (clock,clock_out,clock_out_2,clock_out_4,clock_out_8,clock_out_16,clock_out_32,clock_out_64,clock_out_128);

	input wire clock;
	output wire clock_out;
	output wire clock_out_2;
	output wire clock_out_4;
	output wire clock_out_8;
	output wire clock_out_16;
	output wire clock_out_32;
	output wire clock_out_64;
	output wire clock_out_128;

	assign clock_out = clock;
	half_freq freq_2(.freq_in(clock), .freq_out(clock_out_2));
	half_freq freq_4(.freq_in(clock_out_2), .freq_out(clock_out_4));
	half_freq freq_8(.freq_in(clock_out_4), .freq_out(clock_out_8));
	half_freq freq_16(.freq_in(clock_out_8), .freq_out(clock_out_16));
	half_freq freq_32(.freq_in(clock_out_16), .freq_out(clock_out_32));
	half_freq freq_64(.freq_in(clock_out_32), .freq_out(clock_out_64));
	half_freq freq_128(.freq_in(clock_out_64), .freq_out(clock_out_128));
	

endmodule

// ***********************
//
// Делитель частоты на два
//
// ***********************
module half_freq (freq_in, freq_out);

	input wire freq_in;						// Входной клок
	output reg freq_out;						// Выходной клок
	reg state;									// счетчик

	always @(posedge freq_in)
	begin

		if (state)				// Если на входе 1 и счетчик - 1, сбрасываем счетчик и инвертируем состояние сигнала.
		begin
			state <= 1'b0;
			freq_out <= ~freq_out;
		end
		else
		begin										// Если счетчик не единица, добавляем и инвертируем частоту
			state <= state + 1'b1;
			freq_out <= ~freq_out;
		end
	end
endmodule

vlog -reportprogress 300 -work work {E:/FPGA projects/LED_blink/LED_blink.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:43:09 on Dec 28,2017
# vlog -reportprogress 300 -work work E:/FPGA projects/LED_blink/LED_blink.v 
# -- Compiling module test
# -- Compiling module root
# -- Compiling module half_freq
# 
# Top level modules:
# 	test
# End time: 17:43:09 on Dec 28,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim work.root
# End time: 17:43:25 on Dec 28,2017, Elapsed time: 0:01:33
# Errors: 5, Warnings: 0
# vsim work.root 
# Start time: 17:43:25 on Dec 28,2017
# Loading work.root
# Loading work.half_freq
add wave -position insertpoint  \
sim:/root/clock_out

`timescale 1ns / 10ps
module test();
// constants                                           
// general purpose registers
//reg eachvec;
// test vector input registers
reg clock;
// wires                                               
wire clock_out;
wire clock_out_2;
wire clock_out_4;
wire clock_out_8;
wire clock_out_16;
wire clock_out_32;
wire clock_out_64;
wire clock_out_128;

root root_test (
	.clock(clock),
	.clock_out(clock_out),
	.clock_out_2(clock_out_2),
	.clock_out_4(clock_out_4),
	.clock_out_8(clock_out_8),
	.clock_out_16(clock_out_16),
	.clock_out_32(clock_out_32),
	.clock_out_64(clock_out_64),
	.clock_out_128(clock_out_128)
);
initial                                                
begin                                                  
	clock = 0;
$display("Running testbench");                       
end                                                    

always                                                 
begin                                                  
	#5 clock = ~clock;
end                                                    
endmodule

module test (clock, data_out);

	input wire clock;

	output reg [7:0] data_out;

	reg [7:0] res;
	reg [25:0] count;

	always @( posedge clock ) begin
	
		count <= count+1;
		
		case ( count )
		
			25'b1000000000000000000000000: res <= res+1;
		
		endcase
		
		data_out <= ~res;
	
	end

endmodule

`timescale 10 ns/ 1 ps

module test_vlg_tst();
reg clock;
wire [7:0]  data_out;

test i1 (
	.clock(clock),
	.data_out(data_out)
);

initial begin
	clock = 0;
	$display("Running testbench");
end                                                    

always begin
	#2 clock = ~clock;
end
                                        
endmodule