ТЕМА:

// video signal parameters, default 1440x900 60Hz
	parameter horz_front_porch = 80;
	parameter horz_sync = 152;
	parameter horz_back_porch = 232;
	parameter horz_addr_time = 1440;
	
	parameter vert_front_porch = 3;
	parameter vert_sync = 6;
	parameter vert_back_porch = 25;
	parameter vert_addr_time = 900;

VGA ADV7123	 //выписка из даташта на демоплату.								
HS	        B4								
VS	        A4								
VGA-CLK	M4								
BLANK	H2								
R2	        A3								
R3	        B3								
R4	        E4								
R5	        E3								
R6	       G4								
R7	       G3								
... и далее вся R2R матрица. 							
							

	// video signal parameters, default 1024x768 60Hz  clok 65 MHz
	parameter horz_front_porch = 24;      //H Front Porch = 0.369; // (usec) = 3 chars = 24 Pixels
	parameter horz_sync = 136;            //Hor Sync Time = 2.092; // (usec) = 17 chars = 136 Pixels
	parameter horz_back_porch = 160;      //H Back Porch = 2.462; // (usec) = 20 chars = 160 Pixels
	parameter horz_addr_time = 1024;
	
	parameter vert_front_porch = 3;       // V Front Porch = 0.054; // (msec) = 3 lines
	parameter vert_sync = 6;              //Ver Sync Time = 0.107; // (msec) = 6 lines
	parameter vert_back_porch = 29;       //V Back Porch = 0.600; // (msec) = 29 lines
	parameter vert_addr_time = 768; 

///////////////////////////////////////////////////////////////
//module which generates video sync impulses
///////////////////////////////////////////////////////////////

module hvsync (
	// inputs:
	input wire pixel_clock,

	// outputs:
	output reg hsync,
	output reg vsync,

	//high-color test video signal
	output  [7:0]R,
	output  [7:0]G,
	output  [7:0]B
	);
	
	// video signal parameters, default 1024x768 60Hz
	parameter horz_front_porch = 24;      //H Front Porch = 0.369; // (usec) = 3 chars = 24 Pixels
	parameter horz_sync = 136;            //Hor Sync Time = 2.092; // (usec) = 17 chars = 136 Pixels
	parameter horz_back_porch = 160;      //H Back Porch = 2.462; // (usec) = 20 chars = 160 Pixels
	parameter horz_addr_time = 1024;
	
	parameter vert_front_porch = 3;       // V Front Porch = 0.054; // (msec) = 3 lines
	parameter vert_sync = 6;              //Ver Sync Time = 0.107; // (msec) = 6 lines
	parameter vert_back_porch = 29;       //V Back Porch = 0.600; // (msec) = 29 lines
	parameter vert_addr_time = 768;       
	
	//variables	
	reg [11:0]pixel_count = 0;
	reg [11:0]line_count = 0;

reg hvisible = 1'b0;
reg vvisible = 1'b0;

//synchronous process
always @(posedge pixel_clock)
begin
	hsync <= (pixel_count < horz_sync);
	hvisible <= (pixel_count >= (horz_sync+horz_back_porch)) && 
		(pixel_count < (horz_sync+horz_back_porch+horz_addr_time));
	
	if(pixel_count < (horz_sync+horz_back_porch+horz_addr_time+horz_front_porch) )
		pixel_count <= pixel_count + 1'b1;
	else
		pixel_count <= 0;
end

always @(posedge hsync)
begin
	vsync <= (line_count < vert_sync);
	vvisible <= (line_count >= (vert_sync+vert_back_porch)) && 
		(line_count < (vert_sync+vert_back_porch+vert_addr_time));
	
	if(line_count < (vert_sync+vert_back_porch+vert_addr_time+vert_front_porch) )
		line_count <= line_count + 1'b1;
	else
		line_count <= 0;
end

reg [7:0] bar;
reg [2:0] color;

wire visible; assign visible = hvisible & vvisible;
wire rvisible; assign rvisible = pixel_count[6];
wire gvisible; assign gvisible = pixel_count[7];
wire bvisible; assign bvisible = pixel_count[8];

assign B = color[0] ? 8'hFF : 8'h0;
assign R = color[1] ? 8'hFF : 8'h0;
assign G = color[2] ? 8'hFF : 8'h0;
  
//output wire [23:0] rgb = blank ? {blue[7:0], green[7:0], red[7:0]} : 24'b0;
 
always @(posedge pixel_clock)
begin
/*
    if (!blank)
    begin
        bar <= 8'b0;
        color <= 3'b111;
    end
        else 
		  */
		  if (bar < 8'd210)
                bar <= bar + 1'b1;
                else
                    begin
                        bar <= 8'b0;
                        color <= color - 1'b1;
                    end
         
         
end

/*
always @*
begin
	if(visible & rvisible)
		r = pixel_count[5:1];
	else
		r = 0;

		if(visible & gvisible)
		g = pixel_count[5:0];
	else
		g = 0;

	if(visible & bvisible)
		b = pixel_count[5:1];
	else
		b = 0;
end
*/


endmodule

module hvsync_ex (
    // inputs:
    input wire char_clock,
 
    // outputs:
    output reg [11:0]char_count_, //post reg
    output reg [11:0]line_count_, //post reg
	
	output reg [7:0]red,
	output reg [7:0]green,
	output reg [7:0]blue,
	
    output reg hsync,
    output reg vsync,
	output reg blank
    );
 
//VGA Standart
`define h_visible_area  1024
`define h_front_porch   24
`define h_sync_pulse    136
`define h_back_porch    160
 
`define v_visible_area  768
`define v_front_porch   3
`define v_sync_pulse    6
`define v_back_porch    29
 
//variables
reg [11:0]char_count;
reg [1:0]pixel_state;
reg [11:0]line_count;
reg [1:0]line_state;
 
reg end_of_line;
reg end_of_frame;
 
//permanent comb computations:
always @*
begin
    //horizontal processing
    if(char_count < `h_visible_area)
        pixel_state = 0; //active video
    else
    if(char_count < `h_visible_area + `h_front_porch)
        pixel_state = 1; //front porch
    else
    if(char_count < `h_visible_area + `h_front_porch + `h_sync_pulse)
        pixel_state = 2; //hsync impuls
    else
        pixel_state = 3; //back porch
 
    if(char_count < `h_visible_area + `h_front_porch + `h_sync_pulse + `h_back_porch)
        end_of_line = 0;
    else
        end_of_line = 1;
 
    //vert processing
    if(line_count < `v_visible_area)
        line_state = 0; //active video lines
    else
    if(line_count < `v_visible_area + `v_front_porch)
        line_state = 1; //front porch
    else
    if(line_count < `v_visible_area + `v_front_porch + `v_sync_pulse)
        line_state = 2; //vsync impuls
    else
        line_state = 3; //front porch
 
    if(line_count < `v_visible_area + `v_front_porch + `v_sync_pulse + `v_back_porch)
        end_of_frame = 0;
    else
        end_of_frame = 1;            
end
 
//synchronous process
always @(posedge char_clock)
begin
    hsync <= (pixel_state!=2'b10);
    vsync <= (line_state!=2'b10);
    blank <= (pixel_state==2'b0 && line_state==2'b0);
 
    //char_count_ <= char_count;
    line_count_ <= line_count;
 
    if(end_of_line)
    begin
        char_count <= 0;
        char_count_ <= 0;
 
        if(end_of_frame)
            line_count <= 0;
        else
            line_count <= line_count + 1'b1;
    end
    else
    begin
        char_count <= char_count + 1'b1;
        if (pixel_state==2'b0)
			char_count_ <= char_count_ + 1'b1;
    end
end

//test generation!!!

always @(posedge char_clock)
begin
	if (blank)
	begin
		red <= (char_count_ ^ line_count_) >> 4;
		green <= (char_count_ ^ line_count_) >> 2;
		blue <= (char_count_ ^ line_count_);
	end	
end
 
endmodule