ТЕМА:

module point
(
	input clock,
	input vsync, hsync,
	input[11:0] har_count, line_count,
	
	
	output reg video,
	output reg[7:0] R, G, B

);
reg[7:0] als, bls, cls;
//reg blanc;
//assign blanc = (vsync == 2'b0 && hsync == 2'b0)? 1 : 0;
always @(posedge clock)
	begin
		if(vsync == 2'b0 && hsync == 2'b0)
			begin als = 0; bls = 0; cls = 0; end 
		
	 
		if(line_count == 300)
		begin 
			als = als + 1;
			R= als;
			if(har_count >= 100)
				begin  bls = bls + 1; G = bls; end 
			if(har_count >= 200)
				begin cls = cls+1; B = cls; end 
				
				
		end
		else
			begin 
				R = 0;
				G = 0;
				B = 0;
			end 
	
	end 


endmodule 

module mul(
   input  [31:0]  A,
   input  [31:0]  B,
   output [63:0]  C
   );
   
   wire [63:0] line0  = A[0]  ? { 32'h0, B        } : 64'h00;
   wire [63:0] line1  = A[1]  ? { 31'h0, B, 1'h0  } : 64'h00;
   wire [63:0] line2  = A[2]  ? { 30'h0, B, 2'h0  } : 64'h00;
   wire [63:0] line3  = A[3]  ? { 29'h0, B, 3'h0  } : 64'h00;
   wire [63:0] line4  = A[4]  ? { 28'h0, B, 4'h0  } : 64'h00;
   wire [63:0] line5  = A[5]  ? { 27'h0, B, 5'h0  } : 64'h00;
   wire [63:0] line6  = A[6]  ? { 26'h0, B, 6'h0  } : 64'h00;
   wire [63:0] line7  = A[7]  ? { 25'h0, B, 7'h0  } : 64'h00;
   wire [63:0] line8  = A[8]  ? { 24'h0, B, 8'h0  } : 64'h00;
   wire [63:0] line9  = A[9]  ? { 23'h0, B, 9'h0  } : 64'h00;
   wire [63:0] line10 = A[10] ? { 22'h0, B, 10'h0 } : 64'h00;
   wire [63:0] line11 = A[11] ? { 21'h0, B, 11'h0 } : 64'h00;
   wire [63:0] line12 = A[12] ? { 20'h0, B, 12'h0 } : 64'h00;
   wire [63:0] line13 = A[13] ? { 19'h0, B, 13'h0 } : 64'h00;
   wire [63:0] line14 = A[14] ? { 18'h0, B, 14'h0 } : 64'h00;
   wire [63:0] line15 = A[15] ? { 17'h0, B, 15'h0 } : 64'h00;

   wire [63:0] line16 = A[16] ? { 16'h0, B, 16'h0 } : 64'h00;
   wire [63:0] line17 = A[17] ? { 15'h0, B, 17'h0 } : 64'h00;
   wire [63:0] line18 = A[18] ? { 14'h0, B, 18'h0 } : 64'h00;
   wire [63:0] line19 = A[19] ? { 13'h0, B, 19'h0 } : 64'h00;
   wire [63:0] line20 = A[20] ? { 12'h0, B, 20'h0 } : 64'h00;
   wire [63:0] line21 = A[21] ? { 11'h0, B, 21'h0 } : 64'h00;
   wire [63:0] line22 = A[22] ? { 10'h0, B, 22'h0 } : 64'h00;
   wire [63:0] line23 = A[23] ? {  9'h0, B, 23'h0 } : 64'h00;
   wire [63:0] line24 = A[24] ? {  8'h0, B, 24'h0 } : 64'h00;
   wire [63:0] line25 = A[25] ? {  7'h0, B, 25'h0 } : 64'h00;
   wire [63:0] line26 = A[26] ? {  6'h0, B, 26'h0 } : 64'h00;
   wire [63:0] line27 = A[27] ? {  5'h0, B, 27'h0 } : 64'h00;
   wire [63:0] line28 = A[28] ? {  4'h0, B, 28'h0 } : 64'h00;
   wire [63:0] line29 = A[29] ? {  3'h0, B, 29'h0 } : 64'h00;
   wire [63:0] line30 = A[30] ? {  2'h0, B, 30'h0 } : 64'h00;
   wire [63:0] line31 = A[31] ? {  1'h0, B, 31'h0 } : 64'h00;

   wire [63:0]    line0_0  = line0 + line1;
   wire [63:0]    line0_1  = line2 + line3;
   wire [63:0]    line0_2  = line4 + line5;
   wire [63:0]    line0_3  = line6 + line7;
   wire [63:0]    line0_4  = line8 + line9;
   wire [63:0]    line0_5  = line10 + line11;
   wire [63:0]    line0_6  = line12 + line13;
   wire [63:0]    line0_7  = line14 + line15;
   wire [63:0]    line0_8  = line16 + line17;
   wire [63:0]    line0_9  = line18 + line19;
   wire [63:0]    line0_10 = line20 + line21;
   wire [63:0]    line0_11 = line22 + line23;
   wire [63:0]    line0_12 = line24 + line25;
   wire [63:0]    line0_13 = line26 + line27;
   wire [63:0]    line0_14 = line28 + line29;
   wire [63:0]    line0_15 = line30 + line31;

   wire [63:0]    line1_0 =  line0_0  + line0_1;
   wire [63:0]    line1_1 =  line0_2  + line0_3;
   wire [63:0]    line1_2 =  line0_4  + line0_5;
   wire [63:0]    line1_3 =  line0_6  + line0_7;
   wire [63:0]    line1_4 =  line0_8  + line0_9;
   wire [63:0]    line1_5 =  line0_10 + line0_11;
   wire [63:0]    line1_6 =  line0_12 + line0_13;
   wire [63:0]    line1_7 =  line0_14 + line0_15;

   wire [63:0]    line2_0 =  line1_0  + line1_1;
   wire [63:0]    line2_1 =  line1_2  + line1_3;
   wire [63:0]    line2_2 =  line1_4  + line1_5;
   wire [63:0]    line2_3 =  line1_6  + line1_7;

   wire [63:0]    line3_0 =  line2_0  + line2_1;
   wire [63:0]    line3_1 =  line2_2  + line2_3;
   
   assign C = line3_0  + line3_1;

endmodule