ТЕМА: Вопросы по языку Verilog

for (j=0; j < 400; j=j+1)
begin
	always @ (posedge clk);
	ram1[i] = ram1[i] + datain;
end

always @ (posedge clk)
begin

end

always @ (posedge clk)
begin
  i=>i+1;
  if (i<400)    ram1[i] = ram1[i] + datain;
end

// run once
initial
begin
	wrEna=1
	i=0
	j=0
end

// write/add cycles
always @ ((posedge clk) & wrEna)
begin
	// if first = write, else accumulate
	if (j=0) 
	begin
		ram1 [i] = datain;
		i = i + 1;
	end
	else if ((i<400) and (j<10))
	begin 
		ram1 [i] = ram1 [i] + datain;
		i = i + 1;
	end
	else if ((i=400) and (j<10))
	begin 
		j = j + 1;
		i = 0;
	end
	else if (j>9)
	begin
		wrEna = 0;
		j = 0;
		i = 0;
	end
end