ТЕМА: Вопросы по языку Verilog

module mdss(datain, dataout, clk, read, dt1, dt2);
// i/o 's
input [10:0] datain;
input clk;
input read;
output reg [14:0] dataout;
output reg [14:0] dt1;
output reg [14:0] dt2;

// internal wires & reg's
reg [14:0] ram1 [0:399];
reg [14:0] ram2 [0:399];
reg [8:0] i,k,l;
reg [3:0] j;
reg copyEna, reading, copied, rdstart;

// run once
initial
begin
i <= 0;
j <= 0;
k <= 0;
l <= 0;
copyEna <= 0;
copied <= 0;
reading <= 0;
end

// 1 // write/add cycles
always @ ( posedge clk )
begin
// if it's 0 of 9 (first) 400-iteration cycle? -> write data in ram1
if (j == 0)
begin
if (i < 399)
begin
ram1 <= datain;
i <= i + 1;
end
else if (i >= 399)
begin
ram1 [399] <= datain;
i <= 0;
j <= j + 1;
end
end
// if not -> accumulate data in ram1
if ((j < 10) && (j > 0))
begin
if (i < 399)
begin
ram1 <= ram1 + datain;
i <= i + 1;
end
else if (i >= 399)
begin
if (j >= 9)
begin
ram1 [399] <= ram1 [399] + datain;
i <= 0;
j <= 0;
end
else if (j < 9)
begin
ram1 [399] <= ram1 [399] + datain;
i <= 0;
j <= j + 1;
end
end
end

if (i==0) dt1 = ram1 [0];
else dt1 = ram1 [i-1];

if ( copied == 1 )
begin
if (i==0) dt2 = ram2 [0];
else dt2 = ram2 [i-1];
end
end

// 3 // 400 copying cycles from ram1 to ram2
always @ ( posedge clk )
begin
// if it's 9 of 9 (last) 400-iteration cycle? -> enable copying
if ((j==9) && (i > 1))
begin
copyEna <= 1;
end

if (copyEna && !reading)
begin
if (k<400)
begin
ram2 [k] <= ram1 [k];
k <= k + 1;
end
// if k=400 ? -> data copied to ram2, disable copying;
else if (k>=400)
begin
copyEna <= 0;
k = 0;
copied = 1;
end
end
end

// 4 // Read from ram2
always @ ( posedge clk )
begin
if (read) rdstart = 1;
if (rdstart && !copyEna && copied)
begin
reading <= 1;
if (l<400)
begin
dataout <= ram2 [l];
l <= l + 1;
end
else if (l==400)
begin
reading <= 0;
l <= 0;
rdstart <= 0;
end
end
end

endmodule