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Leka
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Не в сети
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Живу я здесь
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С mass storage потом пожно будет поэкспериментировать. Но тут HS режим нужен, иначе смысла нет.
Кусок из проекта, без трекера. Посылает инициализирующие пакеты (с ожиданием "EOP"), потом в цикле посылает "IN". Это только для экспериментов(с клавиатурой), для рабочего варианта надо все переделать. reg [31:0] sof0 = {8'h10,8'h00,8'hA5,8'h80};
reg [31:0] sof1 = {8'hE8,8'h01,8'hA5,8'h80};
reg [31:0] sof2 = {8'hA8,8'h02,8'hA5,8'h80};
reg [31:0] sof3 = {8'h50,8'h03,8'hA5,8'h80};
reg [31:0] setup1 = {8'h10,8'h00,8'h2D,8'h80};
reg [31:0] setup2 = {8'h28,8'h04,8'h2D,8'h80};
reg [31:0] in1 = {8'h10,8'h00,8'h69,8'h80};
reg [31:0] in2 = {8'h28,8'h04,8'h69,8'h80};
reg [31:0] in3 = {8'h01,8'h04,8'h69,8'h80};
reg [31:0] in4 = {8'h98,8'h84,8'h69,8'h80};
reg [15:0] ack = {8'hD2,8'h80};
reg [95:0] data0 = {8'h94,8'hDD,8'h00,8'h40,8'h00,8'h00,8'h01,8'h00,8'h06,8'h80,8'hC3,8'h80};
reg [95:0] data1 = {8'h70,8'hEB,8'h00,8'h00,8'h00,8'h00,8'h00,8'h04,8'h05,8'h00,8'hC3,8'h80};
reg [95:0] data2 = {8'h25,8'h27,8'h00,8'h00,8'h00,8'h00,8'h00,8'h01,8'h09,8'h00,8'hC3,8'h80};
reg [95:0] sr;
reg [17:0] step;
reg b, out;
`define sof0 5'd0
`define sof1 5'd17
`define sof2 5'd18
`define sof3 5'd19
`define eop 5'd20
`define ms10 5'd1
`define ms1 5'd2
`define goto 5'd3
`define ack 5'd4
`define se 5'd5
`define pn 5'd6
`define zz 5'd7
`define s1 5'd8
`define s2 5'd9
`define d0 5'd16
`define d1 5'd10
`define d2 5'd11
`define i1 5'd12
`define i2 5'd13
`define i3 5'd14
`define i4 5'd15
//.setup 00 10 .data0 00 05 04 00 00 00 00 00 EB 70 ..ack .in 00 10 ..data1 00 00 .ack
//.setup 04 28 .data0 00 09 01 00 00 00 00 00 27 25 ..ack .in 04 28 ..data1 00 00 .ack
//.in 04 01 ..nak .in 04 01 ..nak .in 84 98
`define SZ 60
reg [5:0] pc = `SZ;
reg [`SZ:0][4:0] pm = {
`ms10, `se, `pn,
`sof0, `se, `pn, `ms1,
`sof1, `se, `pn,
`s1, `se, `pn,
`d1, `se, `pn,
`zz, `eop, `pn,
`i1, `se, `pn,
`zz, `eop, `pn,
`ack, `se, `pn,
`s2, `se, `pn,
`d2, `se, `pn,
`zz, `eop, `pn,
`sof2, `se, `pn, `ms1,
`i2, `se, `pn,
`zz, `eop, `pn,
`ack, `se, `pn,
`i4, `se, `pn,
`zz, `eop, `pn,
`ack, `se, `pn,
`ms1,
`goto
};
`define cmd pm[pc]
reg [3:0] cnt12M;
wire clk12M = (cnt12M == 5);
always@(posedge clk)
if(cnt12M == 9) cnt12M <= 0;
else cnt12M <= cnt12M + 1;
reg [7:0] cmdcnt;
always@(posedge clk)if(clk12M)begin
if(out)begin b <= b ^ ~sr[0]; dp <= b ^ ~sr[0]; dn <= ~(b ^ ~sr[0]); sr <= {1'b0, sr[95:1]}; end
if(step != 0) step <= step - 1;
else begin
oe <= 1; out <= 0;
pc <= pc - 1;
if(`cmd == `goto) begin pc <= pc + 10; end
if(`cmd == `ms10) begin step <= 120000; dp <= 0; dn <= 0; end
if(`cmd == `ms1) begin step <= 12000; dp <= 1; dn <= 0; end
if(`cmd == `se) begin step <= 2; dp <= 0; dn <= 0; end
if(`cmd == `pn) begin dp <= 1; dn <= 0; b <= 1; end
if(`cmd == `zz) begin oe <=0; if(!((p == 0)&(n == 0))) pc <= pc; end
if(`cmd == `eop) begin oe <=0; if((p == 0)&(n == 0)) pc <= pc; end
if(`cmd == `s1) begin sr <= setup1; step <= 32; out <= 1; end
if(`cmd == `s2) begin sr <= setup2; step <= 32; out <= 1; end
if(`cmd == `d0) begin sr <= data0; step <= 96; out <= 1; end
if(`cmd == `d1) begin sr <= data1; step <= 96; out <= 1; end
if(`cmd == `d2) begin sr <= data2; step <= 96; out <= 1; end
if(`cmd == `i1) begin sr <= in1; step <= 32; out <= 1; end
if(`cmd == `i2) begin sr <= in2; step <= 32; out <= 1; end
if(`cmd == `i3) begin sr <= in3; step <= 32; out <= 1; end
if(`cmd == `i4) begin sr <= in4; step <= 32; out <= 1; end
if(`cmd == `sof0) begin sr <= sof0; step <= 32; out <= 1; end
if(`cmd == `sof1) begin sr <= sof1; step <= 32; out <= 1; end
if(`cmd == `sof2) begin sr <= sof2; step <= 32; out <= 1; end
if(`cmd == `sof3) begin sr <= sof3; step <= 32; out <= 1; end
if(`cmd == `ack) begin sr <= ack; step <= 16; out <= 1; end
end
endclk - 120MHz.
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